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Manufacturing method of semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, transistors, etc., can solve problems such as difficulty in forming overlaps

Inactive Publication Date: 2004-05-19
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, it is difficult to form the gate electrode 106 with n - Layer 115 Overlap

Method used

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  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device
  • Manufacturing method of semiconductor device

Examples

Experimental program
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Embodiment 1

[0033] In this embodiment, a case where a BPSG mold is used as an ion implantation mask instead of a protective film layer will be described.

[0034] figure 1 (a) to (f) are the n steps from the manufacturing process of the semiconductor device of the first embodiment to the formation of the LDD structure. - Schematic cross-sectional view up to the layer process.

[0035] First, in figure 1 In the process shown in (a), a p-type region 2 with a width of 0.5 μm and an n-type region 3 located on the side of the p-type region 2 are formed on the upper part of the silicon substrate 1, and the p-type region 2 and the n-type region 3 are formed. Insulation film 4 is used for element isolation.

[0036] Then, a gate insulating film 5 having a thickness of 5 nm was formed on the p-type region 2 of the silicon substrate 1 by thermal oxidation. Then, a polysilicon film (not shown) is formed on the gate insulating film 5 by CVD, and a protective film (not shown) is formed on the poly...

Embodiment 2

[0046] In this embodiment, a case where a BPSG film having corners rounded by an etching process is used as an ion implantation mask will be described.

[0047] image 3 (a) to (c) are n steps from the manufacturing process of the semiconductor device of the embodiment to the formation of the LDD structure. - Schematic cross-sectional view up to the layer process.

[0048] First, in image 3 In the process shown in (a), in the same manner as in Example 1, a p-type region 2 and an n-type region 3 with a width of 0.5 μm are formed on the upper portion of the silicon substrate 1, and a p-type region 2 and an n-type region 3 are provided. Insulation film 4 is used for element isolation. Then, a gate insulating film 5 with a thickness of 5 nm and a gate electrode 6 with a gate length of 0.15 μm and a thickness of 0.2 μm were formed on the p-type region 2 . Then, the upper surface of p-type region 2 in silicon substrate 1 is opened, and hard mask 21a covering the region from the...

Embodiment 3

[0055] In Example 3, a BPSG film having corners rounded by a heat treatment process is used as an ion implantation mask.

[0056] Figure 5 (a) to (c) are the steps from n to the formation of the LDD structure in the manufacturing process of the semiconductor device of the third embodiment. - Schematic cross-sectional view up to the layer process.

[0057] First, in Figure 5 In the step shown in (a), p-type region 2 , n-type region 3 , and insulating film 4 for element isolation were formed on the upper portion of silicon substrate 1 in the same manner as in Example 1. Then, a gate insulating film 5 with a thickness of 5 nm and a gate electrode 6 with a gate length of 0.15 μm and a thickness of 0.2 μm were formed on the p-type region 2 . Then, a hard mask 31 a is formed on the upper surface of the p-type region 2 in the silicon substrate 1 to cover the region from the upper surface of the n-type region 3 through the upper surface of the insulating film 4 for element isolat...

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Abstract

A hard mask 21a which has an opening for exposing a p-type region 2 defined in a silicon substrate 1 and is made of, for example, a BPSG film is formed. Then, the hard mask 21a is subjected to isotropic etching using argon gas, to have its edge rounded off, thereby forming an implantation hard mask21 having a tapered edge. Subsequently, large-angle-tilt ion implantation of an n-type impurity is performed using the implantation hard mask 21 as a mask, thereby forming an n<-> layer 13 having an LDD structure. Thereafter, the implantation hard mask 11 is removed. In this manner, it is possible to perform large-angle-tilt ion implantation using an implantation mask thinner than a conventional implantation mask.

Description

technical field [0001] The present invention relates to a method of manufacturing a semiconductor device including a step of implanting ions into a semiconductor layer from an oblique direction. Background technique [0002] Conventionally, as a method of forming an impurity diffusion layer in a semiconductor layer, a method of implanting ions from a direction inclined by about 40 degrees with respect to the normal direction of the upper surface of the semiconductor layer (hereinafter referred to as oblique ion implantation method) is known. The oblique ion implantation method can be employed, for example, in a transistor manufacturing process having an LDD (Lightly Drain Structure) structure. In this process, by obliquely implanting ions into the semiconductor layer after the gate electrode is formed, n - layer. This method is disclosed in Japanese Patent Application Laid-Open Publication No. 6-295875 (pages 3-5, figure 1 ). [0003] Refer to the attached Figure 9 , t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/265H01L21/266H01L21/336H01L29/78
CPCH01L29/7835H01L29/66492H01L21/26586H01L29/7833H01L29/6659H01L21/26513
Inventor 半田崇登海本博之
Owner PANASONIC CORP
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