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Cmbined circuit equipment checking method based on satisfiability

A testing method and combined circuit technology, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve complex problems

Active Publication Date: 2005-01-05
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Abstract
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Problems solved by technology

In addition, when deriving internal equivalence, it is necessary to make full use of known equivalence relations and prevent the verification process from becoming too complicated later

Method used

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  • Cmbined circuit equipment checking method based on satisfiability
  • Cmbined circuit equipment checking method based on satisfiability
  • Cmbined circuit equipment checking method based on satisfiability

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Experimental program
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Embodiment Construction

[0025] The meanings of each label in the accompanying drawings are as follows:

[0026] 1: The corresponding box represents the design specification circuit.

[0027] 2: XOR gate.

[0028] 3: The corresponding box represents the implementation circuit.

[0029] 4: AND gate.

[0030] 5: OR gate.

[0031] 6: NOT gate.

[0032] In addition, with Figure 4 Among them, S1, S2, S3, S4, and S5 respectively correspond to the five steps in the technical invention scheme.

[0033] attached figure 1 Among them, (1) represents the design specification circuit. (3) represents the implementation circuit. In order to verify the equivalence of two corresponding signals, it is only necessary to connect the two signals to an XOR gate (2), and then prove that the output of the XOR gate is fixed at 0, and the fault cannot be tested. It is worth noting that when using the satisfiability algorithm to verify, it is not necessary to realize this physical connection, but only to construct the c...

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Abstract

The invention relates to designing and testing technology field of very large scale integrating circuit, namely equivalence testing method. The method uses satisfiability arithmetic as the engine, tests the whole circuit design, the method has two segments, the first segment is to determine the candidate equal signal in the two circuits, and through the circuits structure analysis, carries on static sift to the candidate equal signal, the second segment is to realize gain satisfiability method through clause group, and tests the equivalence of the candidate signal. The main character of the invention is: 1) selects the candidate equal signal in the circuit through circuit structure analysis, selects the cut or centralized equal signal dynamically in the process of test, and guarantees the signal is independent from each other. 2) Realizes the satisfiability arithmetic through grouping the clause saves the calculating resources, upgrades the arithmetic performance and the processing ability.

Description

technical field [0001] The invention relates to the technical field of VLSI design verification, in particular to a satisfiability-based equivalence inspection method for combined circuits, especially a formalized verification method for combined circuits. It uses circuit structure analysis to screen candidate equivalent signals inside the circuit, and uses incremental satisfiability algorithm to improve the performance of the combinational circuit equivalence test method, which greatly improves the processing capacity of the method. Background technique [0002] With the increasing scale and complexity of integrated circuit design, the functional verification of the system has become the bottleneck of the entire design process. Simulation is the most common method of functional verification. However, for today's large, complex designs, simulation alone is time-intensive and incomplete, making some marginal design errors difficult to detect. At present, the formal verifica...

Claims

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Application Information

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IPC IPC(8): G06F17/50
Inventor 李光辉李晓维
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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