Design method of 0.35 um LDMOS high vltage power displaying driving element

A design method and display driving technology, applied in the direction of electric solid-state devices, semiconductor devices, static indicators, etc., can solve the problems of large total area of ​​die, large working current, difficulty in shortening channel length, etc.

Inactive Publication Date: 2005-01-12
TSINGHUA UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] b. Double well diffusion is difficult to shorten the channel length, the existing length is 1.5 ~ 3μm
[0014] c. Due to the large working current (150mA) and the large number of devices (more than 100), the total area of ​​the die is too large

Method used

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  • Design method of 0.35 um LDMOS high vltage power displaying driving element
  • Design method of 0.35 um LDMOS high vltage power displaying driving element
  • Design method of 0.35 um LDMOS high vltage power displaying driving element

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Embodiment

[0061] Figure 5 is the actual layout of the driving device composed of 4 0.35μm, LD-NMOS units connected in parallel (for clarity, some details are gated out). The channel length of the unit device is L=0.35μm, the total width W=160μm, and the gate oxide layer d ox =100,open voltage V T =0.7V. At gate voltage V G =4V, leakage current I D = 1mA / μm. 160 rows of drive array, unit area 28×40=1120μm 2 , The total area is 160×28×40=4480×40μm 2 . It can be changed to 160×14×80=2240×80μm according to needs 2 arrangement. In the latter arrangement, the wire current density reaches 1.6×10 6 / cm 2 , But because the duty cycle is less than 0.01, this scheme is feasible.

[0062] The plan view and the cross-sectional structure of LDPMOS are similar, but the doping is different. The most important difference is that the total channel width of the P tube is about 20 μm, which is 1 / 8 of the N tube, because it does not need to bear too much current.

[0063] Figure 6 is The layout of the lead c...

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Abstract

Base on compatible standard 0.5 micro technique, two times of ion implantation in P, N channel regions, and two times of ion implantation in P, N drift regions are added in the invention. The procedures adopted in the invention are as following: reaching thickness in 100 Angstrom of gate oxidizing layer; injecting boron and phosphorus impurities after forming polysilicon gate; forming channels in 0.3-0.4 micro, short drift region and P, N MOS devices through transverse diffusion and self alignment. On P trap, one time of ion implantation in drift region and one time of doping injection in channel region produces PMOS device. One time of ion implantation in P drift region on N trap and one time of doping injection in channel region produces NMOS device. Features are small area of tube core, and large driving current.

Description

Technical field [0001] The design method of 0.35μm LDMOS high-voltage power display drive device belongs to the technical field of high-voltage power display drive device manufacturing, especially the design of high-voltage power display drive technology for organic light emitting diode OLED (Organic Light Emission Diode) black and white and color display screens. Background technique [0002] After searching, in the website of the State Intellectual Property Office, the patent in a similar field is TFT (Thin Film Transistor) LCD (Liquid Crystal Display) drive circuit. The voltage is up to about 70V, and the current is in the milliampere level. Individual patents involve PDP (PlasmaDisplay Panel) drive circuit, high voltage 80V, single tube output current 40mA. [0003] There are no authorized patents related to OLED drive circuits. [0004] Figure 1 is a 2002 article "High-Voltage Device for 0.5μm Standard CMOS Technology" reported, using standard 0.5μm CMOS process to manufactu...

Claims

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Application Information

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IPC IPC(8): G09G3/00H01L21/70H01L51/00
Inventor 王纪民曹林肖文锐
Owner TSINGHUA UNIV
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