Single-chip analog system with multi-processor structure

Abstract

An analog system of single chip-multiple processor structure is featured as connecting general control module separately to preprocessing module, core generating module and test verification module; connecting the preprocessing module simultaneously to core generating module and test verification module; connecting the core generating module to frame structure of CMP system on output module and connecting the test verification module to test verification report of output module.

Description

technical field [0001] The invention belongs to the technical field of computer simulation and emulation, in particular to the simulation and evaluation of an expandable single-chip multiprocessor system. Background technique [0002] Key indicators to measure the performance of a microprocessor include main frequency, power consumption and communication speed. In order to make the processor reach a new level of perfect match between power consumption and performance, one of the methods is to use multi-threading technology, that is, to execute multiple independent instruction sequences in the processor at the same time, so as to increase the resource utilization of the processor per unit time. . The single-chip multi-processor (CMP-Chip Multi-Processor) structure is proposed based on this idea, that is, multiple processor cores are integrated inside the chip, and each thread is smoothly assigned to each processing core, thereby Improve the throughput of microprocessor task...

AI Technical Summary

Problems solved by technology

[0005] Since single-chip multi-processors require good scalability, strong automatic generation capabilities, and good flexibility, most single-chip multi-processor simulation systems are more or less flawed, such as the University of Wisconsin The simplemp developed by the University of California, San Diego, and the simsmt developed by the University of California, San Diego, do not have a component-level accurate simulation mechanism and a precise interrupt simulation mechanism; nor do they have a component-level reusable mechanism, so that when the pipeline changes, the flexibility of the entire system Poor sex

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