Strained FinFET CMOS device structures

Abstract

A semiconductor device structure, includes a PMOS device and an NMOS device disposed on a substrate the PMOS device including a compressive layer stressing an active region of the PMOS device, the NMOS device including a tensile layer stressing an active region of the NMOS device, wherein the compressive layer includes a first dielectric material, the tensile layer includes a second dielectric material, and the PMOS and NMOS devices are FinFET devices.

Description

technical field [0001] The invention relates to a double-gate semiconductor device structure, in particular to a FinFET device. Background technique [0002] Due to the ability to obtain near-ideal sub-threshold slope, absence of body effect, freedom from short-channel effect, and very high current drive capability, the double-gate semiconductor device structure is a promising future generation of microelectronic devices. s Choice. [0003] A technology-related dual-gate device structure is the Fin Field Effect Transistor (FinFET). FinFETs are particularly attractive due to their relative simplicity of fabrication compared to other dual-gate devices. The channels used in FinFETs are thin rectangular Si islands, often called fins. The gate wraps around the fin so that the channel is gated on both sides of the vertical portion of the fin structure, providing gate control over planar single gate MOSFETs. [0004] FinFETs are well known. For example, U.S. Patent No. 6,413,8...

AI Technical Summary

Problems solved by technology

This prior art approach is aimed at improving nFET mobility and thus only achieves limited improvements in CMOS circuits

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