Unlock instant, AI-driven research and patent intelligence for your innovation.

Memory circuit, dynamic and static ram circuit module

A technology of static random access and dynamic random access, which is applied to circuits, electrical components, electric solid-state devices, etc., and can solve problems such as complex production procedures

Inactive Publication Date: 2006-01-18
TAIWAN SEMICON MFG CO LTD
View PDF0 Cites 3 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The thickness of different gate dielectric layers complicates the fabrication process

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Memory circuit, dynamic and static ram circuit module
  • Memory circuit, dynamic and static ram circuit module
  • Memory circuit, dynamic and static ram circuit module

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0037] In order to make the above objects, features and advantages of the present invention more comprehensible, a preferred embodiment will be described in detail below together with the accompanying drawings.

[0038] figure 2 It represents the integrated circuit module of the present invention, in which the gate structures of at least two devices are electrically adjusted to achieve different electrical characteristics. The NMOS transistors 202 and 206 are taken as examples to illustrate this embodiment. The NMOS transistor 202 uses a one-stage gate doping method to form a lightly doped first gate 204 above the first gate dielectric layer 205 . The NMOS transistor 206 uses a two-stage gate doping method to form a heavily doped second gate 208 above the second gate dielectric layer 209 .

[0039] Except for the gate dopant concentration of NMOS transistors 202 and 206, their architectures are identical. When the physical thicknesses of the first and second gate dielectri...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

An integrated circuit is disclosed having one or more devices having substantially similar physical gate electric thicknesses but different electrical gate electric thicknesses for accommodating various operation needs. One or more devices are manufactured with a same mask set using multiple doping processes to generate substantially similar physical gate dielectric thicknesses, but with different electrical gate dielectric thicknesses. The device undergoing multiple doping processes have different dopant concentrations, thereby providing different electrical characteristics such as the threshold voltages.

Description

technical field [0001] The present invention relates to an integrated circuit, and more particularly to a logic memory circuit, which utilizes multi-level doping technology to electrically adjust the characteristics and reduce the size of a metal oxide semiconductor field effect transistor (MOSFET). Background technique [0002] As the size of MOSFETs continues to decrease, the thermal budget, source / drain junction depth, and dopant concentration decrease to mitigate short channel effects. However, this decreasing trend has a limit. If this limit is exceeded, the lower poly gate doping profile will change, inducing an undesired depletion region between the gate electrode and the gate dielectric layer. If the gate dopant concentration is not saturated enough, it will increase the electrical gate dielectric thickness and reduce the MOSFET saturation current. The electrical gate dielectric thickness is the equivalent thickness of the gate dielectric layer under certain electr...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L27/105H01L27/108H01L27/11
CPCH01L29/4916Y10S257/903H01L21/28035H01L27/1104H01L27/10897H01L27/10894H01L21/82345H01L27/11H01L27/1116H01L27/105H01L21/823462H10B12/50H10B12/09H10B10/18H10B10/00H10B10/12
Inventor 廖忠志
Owner TAIWAN SEMICON MFG CO LTD