Bond pad structure

一种接合垫、合金的技术,应用在半导体/固态器件零部件、半导体器件、电气元件等方向,能够解决降低接合可靠性、接合垫间距与尺寸无法进一步缩小、失去与金层线连结等问题,达到增加可靠度、避免失效与接垫剥离的效果

Active Publication Date: 2006-05-10
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This crack can extend into the interior of the gold interlayer dielectric surrounding the uppermost copper-gold layer, causing erosion and layer delamination problems, and will also cause the aluminum bonding pad to peel off from the uppermost copper-gold layer, losing contact with the gold layer. The connection of the wire, thereby reducing the reliability of the joint
In addition, because aluminum bonding pads are susceptible to mechanical stress damage, the pitch and size of the bonding pads cannot be further reduced, which limits the reduction in chip size in the next generation

Method used

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Embodiment Construction

[0032]The present invention provides an improved bond pad structure for integrated circuits. One embodiment of the present invention provides a bonding pad structure, which has a stress buffer layer disposed between an uppermost interconnection metal layer and a bonding pad layer, so as to avoid damage caused by wafer electrical testing (such as wafer The probe test) and the damage caused by the stress of package impact (such as wire bonding, flip-chip packaging or other external forces in the packaging process). The stress buffer layer can be a conductive material, and compared with the material properties of one of the first metal layer and the bonding pad layer, Young's modulus, hardness, strength or toughness of the stress buffer layer (toughness) is larger. In one embodiment of the present invention, a bonding pad structure is provided on an integrated circuit chip having at least one low-k multilayer (dielectric constant substantially less than 3.9), which has a stress ...

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Abstract

This invention relates to one binding pad structure, which has one stress buffer layer between binding pad layer and upper inner connection wire layer to avoid the impact between crystal circle detecting needles on binding pad. The buffer layer is of one conductive material with its dynamic Young's modulus, hardness, intensity or strength larger than those of metal layer or binding pad layer in upper connection layer. Improving stickiness and intensity, it can alter the bottom of buffer layer into various types, such as protective ring, network or locking grid structure and the stress buffer layer can have multiple holes filled with binding pads.

Description

technical field [0001] The present invention mainly relates to a bond pad structure, and more particularly to a bond pad structure having a stress-buffering layer covering an interconnection metal layer to avoid damage caused by wafer electrical testing. (Wafer AcceptanceTest) and the failure caused by the stress of package impact. Background technique [0002] Bonding pads are the interface between an integrated circuit and a device package within a semiconductor die. The bonding pads are connected to contact pads on the IC bonding side of the device package by wire bonding, tape automated bonding, or flip chip bonding techniques. Copper is used as the material for next-generation interconnect gold layers, contacts, and bond pads because of its superior electrical conductivity and mechanical integrity. An insulating material with a dielectric constant as low as possible, such as silicon oxide with a dielectric constant below 3.9, has been used in back-end-of-line (BEOL) i...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/48H01L21/28H01L21/44H01L21/60H01L21/768H01L23/52
CPCH01L24/05H01L24/45H01L24/48H01L2224/02166H01L2224/0401H01L2224/04042H01L2224/05009H01L2224/05083H01L2224/05093H01L2224/05095H01L2224/05096H01L2224/05147H01L2224/05157H01L2224/05166H01L2224/05171H01L2224/05181H01L2224/05184H01L2224/05187H01L2224/05624H01L2224/45124H01L2224/45144H01L2224/45147H01L2224/48463H01L2924/01005H01L2924/01006H01L2924/01012H01L2924/01014H01L2924/01015H01L2924/0102H01L2924/01022H01L2924/01028H01L2924/01029H01L2924/0103H01L2924/01032H01L2924/01033H01L2924/01038H01L2924/0104H01L2924/01046H01L2924/01047H01L2924/01049H01L2924/0105H01L2924/01058H01L2924/01073H01L2924/01074H01L2924/01078H01L2924/01079H01L2924/01082H01L2924/04941H01L2924/04953H01L2924/0496H01L2924/05042H01L2924/10329H01L2924/14H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/01019H01L2224/48624H01L2224/48724H01L2224/48799H01L2224/02125H01L2224/05576H01L2224/05076H01L2224/02126H01L2924/00014H01L2924/01004H01L2924/01077H01L2224/48824H01L2924/00H01L2924/00012H01L2924/01013H01L2924/01025H01L2924/01024
Inventor 黄泰钧姚志翔万文恺
Owner TAIWAN SEMICON MFG CO LTD
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