Strain source-drain CMOS integrating method with oxide separation layer

Abstract

The integration methods include following integrated parts: method for manufacturing PMOS of epitaxial growth of source and drain poles on silicon germanium by using interval layer of oxide and hard mask of polysilicon as mask; method for manufacturing NMOS of epitaxial growth of source and drain poles on silicon carbon; and removing hard mask safely. The method produces strain source and drain CMOS with interval layer of oxide.

Description

technical field [0001] The invention relates to a CMOS manufacturing method, in particular to an integration method of a strained source-drain CMOS with an oxide spacer layer. Background technique [0002] The fabrication process of an integrated circuit includes the formation of a gate pattern of a conductive structure, usually with polysilicon as the gate. In this process, the polysilicon layer is deposited on the substrate, and the single crystal silicon undergoes multiple processes such as implantation and gate oxidation. The polysilicon is then covered with a silicon oxide and / or silicon oxynitride dielectric material. The dielectric layer is photolithographically patterned and etched to form a gate conductive structure pattern. The patterned dielectric material acts as a hard mask to transfer the pattern onto the polysilicon by plasma etching. The hard mask is removed by wet chemicals after polysilicon patterning. [0003] As the critical dimensions become smaller ...

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Problems solved by technology

[0004] The purpose of the present invention is to overcome the problem of corroding spacers and shallow trench isolation regions when removing polysilicon hard masks in the prior art, and to provide CMOS with oxide spacers and strained source and drain, that is, PMOS and epitaxial growth of silicon germanium. Method for growing silicon-carbon NMOS fabrication integrated with safe hardmask removal process

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