Semiconductor element and formation method

Abstract

The present provides a semiconductor element and a forming method thereof. An offset spacer for CMOS transistors and a method of manufacture are provided. A gate electrode is formed on a substrate, and an offset mask layer is formed over the surface of the gate electrode and the substrate. The offset mask may be formed of an oxide layer and acts as a mask during implanting, such as pocket implants and lightly-doped drain implants. A second implant spacer may be formed on top of the offset mask layer adjacent to the gate electrode, and another implant process may be performed to form deeply-doped drain regions. The semiconductor element and the forming method thereof reduces the time and cost spent in depositing and cleaning, besides, the usage of offset mask is controlled more easily.

Description

technical field

[0001] The present invention relates to semiconductor components, in particular to compensation spacers for CMOS transistors. Background technique

[0002] Complementary Metal Oxide Semiconductor Transistor (CMOS) technology is commonly used today in VLSI. Over the past decade, the shrinking of semiconductor dimensions has led to increases in speed, performance, and circuit density, as well as reductions in cost. The continuous reduction of CMOS size is still the main challenge.

[0003] For example, reducing the length of the gate in CMOS, when the gate length is less than 30 nanometers, will increase the interaction between the source / drain region and the channel, and enhance the influence on the channel potential and gate dielectric layer, resulting in The gate electrode is unstable when controlling switching. The phenomenon of reduced gate control caused by a short channel is called the short channel effect.

[0004] An existing method to reduce the s...

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