A vertical dual diffused MOS power device protected by polysilicon ESD structure

A technology of oxide semiconductor and vertical double diffusion, which is applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc. High-level problems, to achieve the effect of preventing damage, improving ESD resistance, and avoiding failure

Inactive Publication Date: 2007-05-16
SICHUAN MIANYANG XINYI TECH
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  • Summary
  • Abstract
  • Description
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AI Technical Summary

Problems solved by technology

However, the multi-finger nMOSFET is designed for lateral MOS devices and cannot be directly applied to VDMOS, and the devices designed by this method occupy a large area, the process operability and controllability are not strong, and the cost is also high

Method used

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  • A vertical dual diffused MOS power device protected by polysilicon ESD structure
  • A vertical dual diffused MOS power device protected by polysilicon ESD structure

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Embodiment Construction

[0027]By adopting the polysilicon ESD protection structure of the invention, an anti-ESD VDMOS power device with excellent performance can be obtained. It can be applied to common power devices such as double diffused field effect transistors, insulated gate bipolar power transistors, and electrostatic induction transistors. Irradiation-hardened VDMOS devices protected by polysilicon ESD structures can be used in aerospace, nuclear environments and other fields that require high device performance. With the development of semiconductor technology, more anti-ESD power devices with high reliability and easier operability can be produced by adopting the invention.

[0028] The VDMOS power device that introduces polysilicon ESD structure protection, as shown in Figure 4, includes the drain 1, n + (or p + ) substrate area 2, n - (or p - ) epitaxial layer 3, p (or n) region 4, n + (or p + ) zone 5, p + (or n + ) region 6, silicon dioxide layer 7, n (or p) doped polysilicon l...

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Abstract

The related vertical double-diffusion MOS power device protected by multicrystal silicon ESD structure introduces PN diode for voltage endurance and discharging ESD current based on general VDMOS. Wherein, the PN junction is formed by different doping multicrystal silicon. This invention can improve device capacity for anti ESD greatly.

Description

technical field [0001] The invention relates to a vertical double-diffused metal oxide semiconductor power device protected by a polysilicon ESD structure, belonging to the technical field of semiconductor power devices. Background technique [0002] Vertical double diffused metal oxide semiconductor (VDMOS) power device is an important basis of power electronics. As a power switch, VDMOS is often used in power integrated circuits and power integrated systems due to its high voltage resistance and low on-resistance. VDMOS is an integral part of the weaponry system. It provides the required form of power supply for electronic equipment and drives for electrical equipment. Almost all electronic equipment and electrical equipment require power VDMOS devices. With the enhancement of anti-radiation ability of VDMOS devices, it is also widely used in aerospace and nuclear environments. FIG. 1 is a schematic diagram of the structure of a conventional VDMOS device. where 1 is the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/49H01L23/60
CPCH01L29/7804H01L2924/0002
Inventor 李泽宏易黎张磊
Owner SICHUAN MIANYANG XINYI TECH
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