Method for manufacturing high-tension film and strain silicon metal oxide semiconductor transistor

A high-tension, strained silicon technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as low tension, reduce the efficiency of ultraviolet technology, affect the drive current of thin-film stress metal oxide semiconductor transistors, etc., and achieve improvement The effect of stress

Inactive Publication Date: 2007-05-23
UNITED MICROELECTRONICS CORP
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Problems solved by technology

[0008] However, since the ultraviolet curing process uses photons to break the Si-H and SiN-H bonds in silicon nitride to increase the tension of the film, its efficiency is bound to be limited by the thickness of the film, that is, the thicker the high-tension film, the thicker the film. Increased tension means lower
Existing methods for making

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  • Method for manufacturing high-tension film and strain silicon metal oxide semiconductor transistor
  • Method for manufacturing high-tension film and strain silicon metal oxide semiconductor transistor
  • Method for manufacturing high-tension film and strain silicon metal oxide semiconductor transistor

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[0025] Please refer to FIG. 4 to FIG. 7. FIG. 4 to FIG. 7 are schematic diagrams of the method of fabricating a high tension film on the surface of an NMOS transistor according to the present invention. As shown in FIG. 4, first, a semiconductor substrate 60, such as a silicon wafer or an SOI substrate, is provided, and the semiconductor substrate 60 includes a gate structure 63. The gate structure 63 includes a gate dielectric layer 64, a gate 66 on the gate dielectric layer 64, a cover layer 68 on the top surface of the gate 66, and an oxide-nitride-oxide Offset spacer (ONO offset spacer) 70. Generally speaking, the gate dielectric layer 64 can be made of silicon oxide or silicon nitride compound formed by processes such as thermal oxidation or deposition, and the capping layer 68 can be a silicon nitride layer for protecting the gate 66 Or composed of polycide. In addition, a shallow trench isolation (STI) 62 surrounds the semiconductor substrate 60 outside the active area (AA)...

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Abstract

The invention relates to a method for preparing high-tension film and stress silicon metal oxide semi-conductor transistor, wherein it comprises that: first providing one semi-conductor substrate, forming one grind, at least one space wall, and one source/drain area on the substrate; then processing n times of depositions, to cover the grid, source/drain area via n layers of high tensile stress film, while each film is treated thermally one time, and n is not lower than 2.

Description

technical field [0001] The invention relates to a method for manufacturing a high tension film, in particular to a method for forming a high tension film on a strained silicon metal oxide semiconductor transistor. Background technique [0002] As semiconductor manufacturing technology becomes more and more sophisticated, integrated circuits have undergone major changes, which has led to a rapid increase in computing performance and storage capacity of computers, and has driven the rapid development of peripheral industries. The semiconductor industry is also developing at the speed of doubling the number of transistors on integrated circuits every 18 months, as predicted by Moore's Law. 90 nanometers (0.09 microns), and 65 nanometers (0.065 microns process) in 2005. [0003] As the semiconductor technology enters the deep sub-micron era, the following technology is becoming increasingly important for improving the electrical performance of the driving circuit of the metal o...

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Application Information

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IPC IPC(8): H01L21/31H01L21/336
Inventor 陈能国蔡腾群廖秀莲黄建中
Owner UNITED MICROELECTRONICS CORP
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