NAND flash memory with densely packed memory gates and fabrication process

Abstract

NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of Invention [0002] This invention pertains generally to semiconductor memory devices and, more particularly, to a NAND flash memory and process of fabricating the same. [0003] 2. Related Art [0004] Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's), cellular phones, and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture. [0005] The traditional NOR-type stack-gate flash memory cell usually has a bit line contact, a source region, a floating gate, and a control gate, with the control gate being positioned directly above the floating gate. Its relatively large cell size prevents it from being used in ...

AI Technical Summary

Benefits of technology

[0011] It is in general an object of the invention to provide a new and improved semiconductor device and process of fabricating the same.

[0012] Another object of the invention is to provide a semiconductor device and process of the above character which overcomes the limitations and disadvantages of the prior art.

Problems solved by technology

Its relatively large cell size prevents it from being used in very high density data storage applications.

However, as the fabrication process advances to very smaller geometry, e.g., tens of nanometer, it is difficult to form a high-voltage coupling ratio which is sufficient for program and erase operations while maintaining a small cell size.

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