Trenched MOSFETS with part of the device formed on a (110) crystal plane

Abstract

This invention discloses an improved MOSFET devices manufactured with a trenched gate by forming part of the trench on a (110) crystal orientation of a semiconductor substrate. The trench is covering with a dielectric oxide layer along the sidewalls and the bottom surface or the termination of the trench formed along different crystal orientations of the semiconductor substrate. Special manufacturing processes such as oxide annealing process, special mask or SOG processes are implemented to overcome the limitations of the non-uniform dielectric layer growth.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The invention relates generally to the semiconductor power devices. More particularly, this invention relates to a novel and improved manufacture method and device configuration for a metal-oxide semiconductor field effect transistor (MOSFET) trenched power device manufactured with part of trench oriented on a (110) crystal plane of a silicon wafer. [0003] 2. Description of the Prior Art [0004] Even though the techniques to provide improved carrier mobility for a P-channel MOSFET, i.e., metal oxide silicon field effect transistors, by forming the transistor on a (110) crystal plane is known, the difficulties of high interface state density is still a limitation for practical implementation of such configurations. Specifically, Sze disclosed in “Physics of Semiconductor Devices” (Wiley-Interscience, 1969, pp. 16, pp. 473) and B. Goebel, D. Schumann, E. Bertagnolli disclosed in IEEE Trans. Electronics Devices, Vol. 48...

AI Technical Summary

Benefits of technology

[0012] It is therefore an object of the present invention to provide a new design and manufacturing methods and device configuration for the power MOSFET devices to take advantages of building the devices on planes of different crystal orientations such that the limitations of the conventional methods can be overcome.

Problems solved by technology

Even though the techniques to provide improved carrier mobility for a P-channel MOSFET, i.e., metal oxide silicon field effect transistors, by forming the transistor on a (110) crystal plane is known, the difficulties of high interface state density is still a limitation for practical implementation of such configurations.

The thicker oxidation thus results in a thick gate oxide layer and lead to an adversely affected higher threshold voltage.

Furthermore, measured data also provide some evidence that thicker oxide layer also causes a degradation of channel mobility.

Furthermore, even when there are several U.S. patents and patent applications that explored the techniques of building the MOS devices on a semiconductor substrate having a (110) crystal orientation, these disclosures are still limited by several technique difficulties due to different practical configuration and manufacture constraints due to the oxide layer thickness variations along different crystal orientations as will be discussed below.

Hasegawa disclose the benefits of building a p-channel MOSFET in a (110) crystal plane, however the configurations and method as disclosed would be too complicate and costly with limited merits for practical application to build a commercial MOSFET product.

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