Metal oxide semiconductor field-effect transistor (MOSFET) and method of fabricating the same

Abstract

A Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) is provided. The MOSFET includes a semiconductor substrate, a device isolating region disposed on a predetermined portion of the semiconductor substrate to define an active region, a source region and a drain region spaced apart from each other about a channel region within the active region, and a gate electrode formed on the active region between the source region and the drain region. Furthermore, the MOSFET also includes a gate insulating layer formed between the active region and the gate electrode. The gate insulating layer includes a central gate insulating layer disposed under central portion of the gate electrode, an edge gate insulating layer disposed under an edge portion of the gate electrode to have a bottom surface level with a bottom of the central gate insulating layer and an upper surface protruding to be higher than an upper surface of the central gate insulating layer.

Description

CROSS-REFERENCE TO RELATED PATENT APPLICATION [0001] This application claims the benefit of Korean Patent Application No. 10-2005-0048820, filed on Jun. 8, 2005, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference herein in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a Metal Oxide Semiconductor (MOS) transistor with a decreased leakage current for the transistor, and a method of fabricating the same. [0004] 2. Description of the Related Art [0005] When fabricating an electric power device such as a Liquid Crystal Display (LCD) Driver IC (“referred to as an LDI”) in a semiconductor IC, a dual gate oxide film is typically employed since a low voltage transistor for logic operated by a low voltage and a transistor for driving an LCD operated by a high voltage should both be embodi...

AI Technical Summary

Benefits of technology

[0021] According to the exemplary embodiments of the present invention, the edge gate insulating layer pattern disposed under an edge portion of the gate electrode is thicker than the central gate insulating layer pattern disposed on the lower central portion of the gate electrode while applying the STI process, thereby alleviating the electric field concentrated on the lower edge portion of the gate electrode to inhibit a leakage current. Additionally, the edge gate insulating layer pattern and the central gate insulating layer of the exemplary embodiments of the invention can be readily fabricated using depositing and etching techniques used during the manufacturing of a semiconductor device.

Problems solved by technology

However, if an STI structure is formed on the lower portion of a gate electrode, certain difficulties may still be arise with the above conventional techniques.

However, the above-stated conventional technique involves the burdensome processing of implanting an impurity ion at a low density before forming the field oxide layer 103 in order to reinforce a junction breakdown voltage on the lower portion of the field oxide layer 103.

Moreover, LOCOS applied with a wet process is employed to thus complicate the processing.

Furthermore, it is also difficult to use the above-mentioned conventional techniques to control the thickness and the length of the field oxide layer 103 which functions as a gate insulating layer.

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