Apparatus and method for signal phase control in an integrated radio circuit

Abstract

An apparatus and method to control signal phase in a radio device includes a phase rotator configured to control a phase of a local oscillator. A phase error determination module is configured to determine phase error information based on received in-phase (I) and quadrature (Q) (IQ) signal values. A phase correction module is configured to derive from the received IQ signal values a correction signal and apply the correction signal to the phase rotator in a path of the local oscillator.

Description

BACKGROUND [0001] 1. Technical Field [0002] The present invention relates to signal processing and more particularly to an apparatus and method for providing signal phase control for an integrated radio receiver or transceiver. [0003] 2. Description of the Related Art [0004] An example radio transmission system in a context illustrating the need for signal phase control and, in particular, carrier phase recovery in a receiver will be described. A block diagram of a typical radio transmission system 10 is shown in FIG. 1. [0005] Referring to FIG. 1, a binary data stream (data) is modulated by a modulator 12 to In-phase and Quadrature (IQ) baseband signal vectors (I and Q, respectively) using a modulation such as Binary Phase Shift Keying (BPSK) or Quadrature Phase Shift Keying (QPSK). The baseband IQ signals control the sign and amplitude of two orthogonal radio-frequency carrier components, one cosine and one sine carrier. The IQ baseband signals are mixed, or multiplied, in mixers ...

AI Technical Summary

Problems solved by technology

This frequency error adds a time varying phase error to the received signal, resulting in a typical rotation of the received I / Q signals around the complex plane at a rate proportional to the difference in frequency between the transmit and receive local oscillators.

This phase rotation presents a problem for the receiver when coherent baseband modulation is used.

Further, due to frequency error, the phase of the received signal varies with time.

This noise penalty arises, since subtraction of the phase between two successive symbols multiples the RMS value of the channel phase noise by 1.414, or 3 dB.

The Costas loop 50 has several disadvantages for use with an integrated radio IC architecture: 1) it requires an analog VCO, which can potentially consume large amounts of power and die area, in addition to adding un-wanted phase noise to the received signal, 2) it has the potential of false-lock, 3) the lock time of the Costas loop system may be excessive for high-speed time-division multiplex (TDM) based physical-layer (PHY) protocols which are typically used in high-speed wireless data transmission systems, and 4) although the Costas loop 50 can be configured to lock to a QPSK signal, the complexity increase is significant.

The introduction of the A / D and digital baseband processing brings its own disadvantages, however, for extremely high data rate systems.

The main disadvantage is the need for high speed A / D converters and correspondingly fast digital-signal processing logic for high data (multiple Gb / s) data rates.

These high rate converters and associated digital signal processing logic can increase the complexity and power of the demodulation system significantly compared to a CDR data-slicer based I / O core running at comparable data rates.

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