Error recovery following speculative execution with an instruction processing pipeline

Active Publication Date: 2008-10-09
ARM LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0011]The present technique recognises that not all of the instructions following the erring (lost) instruction need be flushed. Flushing of instructions dependent upon the erring instruction may be sufficient. The dependency can take a wide variety of different forms such as data dependency, control dependency (e.g. branch dependent) and thread dependency (e.g. belonging to the same thread). Flushing fewer instructions reduces the performance impact of the error.
[0012]More particularly, the present technique recognises that when a speculative execution with error detection and error recovery technique is combined with multi-threaded processing

Problems solved by technology

Such pipeline flushing interrupts the normal processing flow and r

Method used

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  • Error recovery following speculative execution with an instruction processing pipeline
  • Error recovery following speculative execution with an instruction processing pipeline
  • Error recovery following speculative execution with an instruction processing pipeline

Examples

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Example

[0061]FIG. 1 schematically illustrates a data processing system in the form of an integrated circuit for performing data processing operations on data values D under control of a stream of program instructions I. The program instructions I are supplied to an instruction processing pipeline 6 containing a plurality of processing stages. One or more of these stages is a decode stage and an instruction decoder 4 is responsive to program instructions at that decode stage to generate control signals supplied to other portions of the data processing system 2 in order to control and configure them to perform the required data processing operations. Other elements of the data processing system 2 include a register bank 8, a multiplier 10, a shifter 12 and an adder 14. These data processing circuit elements 8, 10, 12, 14 are configured and controlled by the control signals from the decoder 4 to perform the data processing operations required by the program instructions as they are being pass...

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Abstract

An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to the field of data processing systems. More particularly, the present invention relates to data processing systems using speculative execution with error recovery mechanisms within instruction processing pipelines.[0003]2. Description of the Prior Art[0004]It is known within systems such as that described in WO-2004 / 084072 to provide data processing systems with instruction processing pipelines that perform speculative execution based upon processed signal values using the assumption that those signal values are correct and then provide error recovery mechanisms which serve subsequently to detect if the signal values concerned were incorrect and initiate appropriate error recovery actions. These techniques are useful in allowing the data processing system to execute closer to its operational limits (e.g. closer to its maximum clock rate or minimum operating voltage) and thereby achieve im...

Claims

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Application Information

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IPC IPC(8): G06F11/07
CPCG06F9/3842G06F9/3851G06F9/3863G06F9/3867G06F11/0721G06F11/0793
Inventor OZER, EMREDAS, SHIDHARTHABULL, DAVID MICHAEL
Owner ARM LTD
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