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Encapsulation method for packaging semiconductor components with external leads

a technology of semiconductor components and packaging, applied in the direction of semiconductor/solid-state device details, semiconductor devices, electrical apparatus, etc., can solve the problems of reducing productivity, degrading the quality of semiconductor components, and conventional packaging technologies for semiconductor components are still faced with limitations, so as to achieve high density, reduce material consumption, and improve productivity

Active Publication Date: 2011-06-02
ALPHA & OMEGA SEMICON INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

"The present invention provides a method to encapsulate semiconductor components with external leads. The method combines the sawing package method and lead-punching package method, resulting in higher density, lower material consumption, and higher productivity. The method includes steps of providing a lead frame with a plurality of lead frame units arranged in two-dimensional array, attaching a semiconductor chip onto the lead frame and electrically connecting the chip to the leads on the lead frame, encapsulating the chips, leads, and die pads with molding material into plastic encapsulation bars, trimming off the tie bars, plating a metallic layer on the bottom surface of the lead frame, and attaching UV dicing tape. The method improves the soldering quality, saves processing time, and enhances the toughness of the lead frame."

Problems solved by technology

The conventional technologies for packaging the semiconductor components are still faced with limitations due to the facts that the packaging processes require longer processing time and higher fabrication costs.
However, this semiconductor packaging method has the following technical problems.
The sawing process simultaneously saws through the plastic-sealed body and the inner metallic leads resulting in metallic burr and distortion at the tips of the leads or even causing de-lamination between two kinds of material, greatly degrades the quality of semiconductor components.
The longer time required to saw along both horizontal and longitudinal directions leads to lower productivity.
The soldering quality may degrade due to smaller lead surface area available for soldering.
If the semiconductor components are plastic encapsulated by the above lead-punching method, the density of lead frame unit arranged on lead frame is low in order to provide extra space for punching, thus resulting in low material utilization factor and waste.

Method used

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  • Encapsulation method for packaging semiconductor components with external leads
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  • Encapsulation method for packaging semiconductor components with external leads

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Embodiment Construction

[0025]A detailed explanation of this invention is described below by reference to of FIGS. 1 and 2A to 2H, with selected embodiments as examples to illustrate the semiconductor packages according to the methods and configurations disclosed in this invention.

[0026]FIG. 1 is a flow chart to illustrate the processing steps of a packaging method according to an embodiment for this invention to package the semiconductor components with external leads. The method includes the following steps:

[0027]Step 1, chip attachment and wiring on lead frame.

[0028]As shown in FIG. 2A, lead frame 1 includes a plurality of lead frame units arranged in a two dimensional array. Each lead frame unit includes a die pad 11 and a plurality of leads 12 located on two opposite sides of the die pad. For simplicity only two leads (one on each side) are shown. The adjacent lead frame units may be connected via leads 12 in horizontal direction to metallic tie bars 13, and via metallic tie bars 13 and leads 12 in lo...

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Abstract

This invention discloses a method for packaging a semiconductor device with leads extending outside its encapsulation. The method comprises the following steps: Step 1, providing a lead frame comprising a plurality of lead frame units arranged in two dimensional array, each lead frame unit comprising a die pad and a plurality of leads located along two opposite sides of the die pad, attaching a semiconductor chip onto the die pad and electrically connecting the electrodes on each chip to its corresponding leads; Step 2, Encapsulating the chips, the die pads, and the leads with molding material into a plurality of one dimensional plastic encapsulation bars with the leads of each lead frame unit extending out along two opposite sides of the plastic encapsulation bars connecting to a plurality of tie bars substantially parallel to the plastic encapsulation bars; Step 3, Trimming off the tie bars therefore cutting off the connections between the leads to the tie bars while preserving a portion of the leads extending out of the plastic encapsulation bars; and Step 4, Sawing through the plastic encapsulation bars to form a plurality of individual semiconductor components with leads extending outside its encapsulation.

Description

FIELD OF INVENTION[0001]This invention generally relates to the field of semiconductor device package and packaging process. More particularly, the present invention is related to a semiconductor package configuration and manufacturing method by packaging the semiconductor components with external leads.BACKGROUND OF THE INVENTION[0002]The conventional technologies for packaging the semiconductor components are still faced with limitations due to the facts that the packaging processes require longer processing time and higher fabrication costs. The limitations of the conventional technologies can be illustrated by the processes of packaging the semiconductor components as described below.[0003]The first one is sawing method, including following steps: Step 1, Chip attachment. Attach semiconductor chips on pre-platted lead frame with a tape attached on the lead frame back side. The lead frame may comprise of a plurality of lead frame units, with each unit containing a die pad and a p...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/78
CPCH01L21/4842H01L21/561H01L23/3107H01L2924/014H01L2924/01079H01L2924/01082H01L2924/01033H01L24/97
Inventor WANG, LIMINSHI, LEIZHAO, LIANGYE, FENG
Owner ALPHA & OMEGA SEMICON INC