3D interconnect structure comprising fine pitch single damascene backside metal redistribution lines combined with through-silicon vias

Abstract

A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a single damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to three dimensional (3D) packaging, and more particularly to the integration of through-silicon vias (TSVs) into 3D packages.[0003]2. Discussion of Related Art[0004]3D packaging is emerging as a solution for microelectronics development toward system on chip (SOC) and system in package (SIP). In particular, 3D flip chip structures with TSVs have the potential for being widely adopted. TSV 3D packages generally contain two or more chips stacked vertically, with vias through silicon substrates replacing edge wiring to create an electrical connection between the circuit elements on each chip.[0005]The Joint Electron Devices Engineering Council (JEDEC) is currently developing a WideIO standard defining the chip-to-chip landing pad interface for a logic-to-memory interface. Conventionally, the physical locations of TSVs are located directly beneath the landing pad locations on a chip, which tak...

AI Technical Summary

Benefits of technology

The present invention relates to a method of manufacturing a 3D interconnect structure using through-silicon vias (TSVs) and very fine pitch single damascene type backside metal redistribution layers (RDLs). The combination of TSVs and RDLs allows for greater circuit layout flexibility, and the use of copper metal which is not possible with subtractive etching processes for producing aluminum RDL lines. The invention also describes a silicon nitride or silicon carbide passivation layer which separates the backside RDLs from the bulk semiconductor of the thinned device wafer and acts as an etch stop layer during oxide trench etching to form the backside RDLs. The technical effects of the invention include greater circuit layout flexibility, finer pitch RDL architecture, and a hermetically sealed 3D interconnect structure.

Problems solved by technology

Conventionally, the physical locations of TSVs are located directly beneath the landing pad locations on a chip, which takes up a lot of real estate.

These materials are not hermetic, and do not provide a robust passivation layer on the backside of the thinned device wafer.

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