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Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof

a technology for semiconductor devices and tooling, applied in the field of semiconductor device manufacturing, can solve the problems of semiconductor devices as well as cmp pads/brushes being often contaminated, inherently very dirty processes, and fragile structures

Inactive Publication Date: 2014-05-08
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a way to clean semiconductor devices and tools used in manufacturing them. The cleaning solution contains antioxidants and a non-oxidizing acid, and is free of a fluorine-containing compound. This solution effectively removes residues from the semiconductor device or tool during manufacturing. The use of this solution helps to improve the quality and reliability of the finished semiconductor device.

Problems solved by technology

These structures are fragile due to their increasingly small dimensions and the types of materials used to form the structures.
Often BEOL processing includes one or more chemical mechanical planarization (CMP) process steps, which are inherently very dirty processes.
However, the semiconductor devices as well as the CMP pads / brushes are often contaminated with particles of ceria that require removal for successful and efficient device manufacture.
In FEOL processes, the typical cleaning chemistries are not selective enough to differentiate between some of these residues that must be removed or metals and the metals required to remain.
TiN is used as a component of some metal gate structures and any loss of TiN in these metal gate structures can result in an undesirable decrease or change in device performance.

Method used

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  • Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof
  • Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof
  • Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0040]In this example, a comparison was made between prior art cleaning chemistries and a cleaning process with an aqueous cleaning solution in accordance with the present disclosure. A cleaning solution in accordance with the present disclosure, referred to herein as dAS, was compounded in aqueous solution and included 1% (w / w) ascorbic acid in 2% (w / w) sulfuric acid as active agents. The dAS solution was used to clean a substrate including a TiN surface having a defined thickness at room temperature (25° C.) for two different immersion times: 60 seconds and 300 seconds. Following immersions, the substrates were rinsed with deionized water and dried. Thickness of the TiN layer was measured before and after cleaning. The results are shown in Table 1 below.

TABLE 1dAS Cleaning ProcessPre-ImmersionPostThicknessEtch RateThickness ofTimeThickness ofDifference(Å / SampleTiN (Å)(seconds)TiN (Å)(Å)minute)A94.886094.500.380.08B57.9230057.630.290.29

[0041]The results indicate that neither dAS ex...

example 2

[0044]In this example, we have studied the use of hot sulfuric acid as a pre-step to remove organic contamination prior to dAS cleaning. This sequence of hot sulfuric followed by dAS was also evaluated with respect to TiN loss. The process included immersing a substrate including TiN to sulfuric acid at 55° C. for 600 seconds followed by immersion to dAS at 25° C. with a subsequent deionized water rinse and drying process. The results are shown in Table 3 below.

TABLE 3Hot Sulfuric Acid / dAS Cleaning SequenceHotsulfuricaciddASTotal TiNHot sulfuricexposureexposureRemovalacid TiNdAS TiNSample(seconds)(seconds)(Å)Removal (Å)Removal (Å)G60030010.6510.570.08

[0045]As demonstrated above, the exposure of the hot sulfuric acid dominates and / or dictates the TiN removal in this process sequence. The measured TiN loss from only the hot sulfuric acid step is about 10.57 Angstroms and is similar to that observed from the soft SC1 in Example 1 that had a loss of about 10 to 15 angstroms. Thus, a com...

example 3

[0047]In this example, the cleaning solution was used to remove ceria from CMP contaminated pads. The pads were exposed to an aqueous solution of dAS as in example 1 for a period of 600 seconds followed by a 30 second deionized rinsing step.

[0048]FIGS. 1 and 2 provide scanning electron microscopy-energy dispersive spectroscopic (SEM-EDS) data, respectively, of the contaminated pad. As shown, significant deposits of ceria and ceria derivatives on the pad are clearly evident. FIGS. 3 and 4 provide SEM-EDS data, respectively, after cleaning the pad with the aqueous cleaning solution. As clearly demonstrated, no ceria signature is evident indicating that the aqueous cleaning solution was highly effective for removing ceria and ceria derivatives from the contaminated pads.

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Abstract

Cleaning solutions and processes for cleaning semiconductor devices or semiconductor tooling during manufacture thereof generally include contacting the semiconductor devices or semiconductor tooling with an acidic aqueous cleaning solution free of a fluorine containing compound, the acidic aqueous cleaning solution including at least one antioxidant and at least one non-oxidizing acid.

Description

BACKGROUND[0001]The present disclosure generally relates to semiconductor device manufacturing and, more particularly, to the cleaning and removal of residues and / or contaminants formed on the semiconductor device during manufacture.[0002]The integrated circuit manufacturing process can generally be divided into front end of line (FEOL) and back end of line (BEOL) processing. The FEOL processes are focused on fabrication of the different devices that make up the integrated circuit, whereas BEOL processes are focused on forming metal interconnects between the different devices of the integrated circuit. In the FEOL processes, shallow trench isolation structures and gate or memory stacks are typically formed. These structures are fragile due to their increasingly small dimensions and the types of materials used to form the structures. BEOL processes may also have fragile structures such as dual damascene etched openings in low k dielectric materials or polysilicon interconnect lines. ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): C11D7/60C11D10/02
CPCC11D3/042C11D3/2079C11D3/2086C11D7/08C11D7/265C11D7/267C11D2111/22H01L21/02057
Inventor CHHABRA, VISHALECONOMIKOS, LAERTISFITZSIMMONS, JOHN A.HANNAH, JAMESKHOJASTEH, MAHMOUDMUNCY, JENNIFER
Owner GLOBALFOUNDRIES INC