Method for generating design constraints for modules in a hierarchical integrated circuit design system

Abstract

What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a tinting budget by examining said generated arrival times at said block pins.

Description

BACKGROUNDIn Electronic Computer Aided Design (ECAD) software systems, an integrated circuit design specification and implementation data must be stored as a set of database records, and these records have some finite maximum size based on the virtual memory capacity of the computer on which the software is running. In addition, the execution time of the ECAD software normally increases with the size of the design. The data to represent a very large integrated circuit design may be too large to fit in a computer's memory, or the execution time required to design or simulate the entire design may be prohibitive. This is particularly true where the number of components (i.e. gates) and attendant connections within an integrated circuit are in the 10s or 100s of millions or more.Hierarchical decomposition or “partitioning” is a technique which may be used to reduce the complexity of a large integrated circuit design specification so that the memory and / or execution time required to com...

AI Technical Summary

Problems solved by technology

In addition, the execution time of the ECAD software normally increases with the size of the design.

The data to represent a very large integrated circuit design may be too large to fit in a computer's memory, or the execution time required to design or simulate the entire design may be prohibitive.

Otherwise the system may not be able to complete the implementation of some blocks according to their specifications.

The problem is complicated by the fact that this representation must be generated before other modules or the top-level netlist has been completed.

When the timing budget for a module is incomplete, the module cannot be fully designed without its context and the final design is likely to contain errors associated with violated constraints that were omitted from the budget.

When timing budgets are unbalanced, designers are forced to rework the final design to resolve problems that appear during integration of the top level.

This rework often occurs very late in the design process and may require drastic and painful changes.

Failure to generate balanced timing budgets may be seen as a lack of design discipline that has delayed timing closure in design methodologies.

The requirements of completeness and balance make achievability the most challenging aspect of the time budgeting problem.

The difficulty is to create budgets that are achievable while maintaining balance and completeness.

When the timing budget for a module is unachievable, designers are forced into a difficult cycle of iterative implementation and renegotiation of budgets.

The inability to measure achievability is the biggest problem faced by design teams today and is the largest contributor to the failure to achieve timing closure that is experienced in contemporary design methodologies.

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