Semiconductor on insulator vertical transistor fabrication and doping process

Abstract

A process for conformally doping through the vertical and horizontal surfaces of a 3-dimensional vertical transistor in a semiconductor-on-insulator structure employs an RF oscillating torroidal plasma current to perform either conformal ion implantation, or conformal deposition of a dopant-containing film which can then be heated to drive the dopants into the transistor. Some embodiments employ both conformal ion implantation and conformal deposition of dopant containing films, and in those embodiments in which the dopant containing film is a pure dopant, the ion implantation and film deposition can be performed simultaneously.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part of U.S. application Ser. No. 10 / 838,052 filed May 3, 2004 now U.S Pat. No. 7,223,676 entitled LOW TEMPERATURE CVD PROCESS WITH CONFORMALITY, STRESS AND COMPOSITION by Hiroji Hanawa, et al., which is a continuation-in-part of U.S. patent application Ser. No. 10 / 786,410 filed Feb. 24, 2004 now U.S. Pat. No. 6,893,907 entitled FABRICATION OF SILICON-ON-INSULATOR STRUCTURE USING PLASMA IMMERSION ION IMPLANTATION by Dan Maydan et al., which is a continuation-in-part of U.S. patent application Ser. No. 10 / 646,533 filed Aug. 22, 2003 entitled PLASMA IMMERSION ION IMPLANTATION PROCESS USING A PLASMA SOURCE HAVING LOW DISSOCIATION AND LOW MINIMUM PLASMA VOLTAGE by Kenneth Collins et al., which is a continuation-in-part of U.S. patent application Ser. No. 10 / 164,327 filed Jun. 5, 2002 now U.S. Pat. No. 6,939,434 entitled EXTERNALLY EXCITED TORROIDAL PLASMA SOURCE WITH MAGNETIC CONTROL OF ION DISTRIBUTION b...

AI Technical Summary

Benefits of technology

The patent describes a process for making a vertical transistor on a semiconductor-on-insulator wafer. The process involves creating a 3-dimensional structure with a channel and source-drain using a thin gate oxide layer and a conformal thin gate structure. Dopant atoms are then implanted into the structure using a torroidal plasma reactor. The process can also involve depositing a dopant-containing layer onto the structure and then driving the dopant atoms into the structure using a heating step. The technical effects of this process include improved performance and reliability of vertical transistors and better control over dopant concentration and distribution.

Problems solved by technology

Planar transistor structures formed in an SOI island are still limited in their performance by the presence of a PN junction between the source or drain and the surrounding semiconductor material.

However, this technique is not ideal because nearby or neighboring vertical transistor structures may shadow some of the surfaces during ion implantation.

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