Delay circuit device

Abstract

A delay circuit device is described which includes a first delay circuit series that can extract output from any position on a transmission path of a signal, a second delay circuit series that can enter input from any position on a transmission path of a signal, and a control circuit having an input terminal, an output terminal, and an input/output control terminal for signals. The first delay circuit series and the second delay circuit series are arranged such that their signal transmission paths are aligned in opposite directions; the output of the first delay circuit series and the input of the second delay circuit series passing by way of the control circuit and being sequentially connected to each other from the side close to the input of the first delay circuit series and from the side close to the output of the second delay circuit series. A first signal is inputted to the first delay circuit series, a second signal is inputted to the control circuit at an arbitrary subsequent time, and the first signal in the first delay circuit series is transferred to the second delay circuit series.

Description

BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to a semiconductor circuit device, and particularly to a delay circuit device for use in generating transmitting or controlling synchronous signals (hereinafter referred to as "clock pulse").2. Description of the Related ArtAs shown in FIG. 1, a semiconductor circuit device using clock pulses according to the prior art receives an external clock pulse 401 at reception circuit 402, amplifies the clock pulse at an amplification circuit 403, and generates an internal clock pulse 405 for use in circuit 404. As a result, in the process of receiving at reception circuit 402 and amplifying at amplification circuit 403, a delay time 406 is produced between the external clock 401 and the internal clock 402, as shown in FIG. 2. This delay time 406 tends to increase with increased circuit scale of semiconductor circuit devices achieved through progress in manufacturing techniques and the growing diameter of semic...

AI Technical Summary

Benefits of technology

6. Few types of circuits are used, and defective elements can be dealt with easily.

7. Because a totally digital circuit is employed, control can be easily effected through use of a counter, and when controlling a clock of large cycle, the number of times the clock circulates in the delay circuit can be counted using the counter, thereby avoiding a drastic increase in the number of circuits and achieving control over a wide range of cycles.

8. Ease of control allows an inputted external clock that exceeds the range of control to be switched to a circuit that does not pass through the two delay circuit series of the present invention, thereby avoiding malfunctions.

9. Because phase differences can be eliminated in two cycles, a clock pulse may be controlled using the command signals or internal signals of a synchronous memory circuit device, and moreover, the control operation need be effected only when necessary within the overall circuit of a memory circuit device, and during standby, operation can be halted to conserve power.

10. Setting of the duty ratio and clock cycle can be easily effected by regulating the ratio between the delay times of the two delay circuit series.

11. By using a phase comparison circuit, phase difference between an external clock pulse and internal clock pulse can be more accurately matched. Moreover, because the phase is matched in advance even without a phase comparison circuit, phase regulation using phase comparison circuit for correction can be carried out in an extremely short time. In addition, a circuit using a phase comparison circuit enables control over a wide range of frequencies.

Problems solved by technology

1. Time (in excess of several tens of cycles) is required to eliminate the phase difference between the internal clock pulse and external clock pulse.

2. As a result of drawback 1, the PLL must always be operated to provide an internal clock pulse having no phase difference with the external clock pulse at a desired timing, thereby increasing power consumption.

3. Because a voltage-controlled oscillator controls oscillation by voltage, the amplitude of the control voltage drops with a decrease in power source voltage, thereby degrading the accuracy of the controlled frequency.

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