Non-volatile memory with improved coupling rate and its making method

Abstract

By increasing the overlapping area of control grid and floating gate, a storage device attains the increase of the coupling ratio of control grid to floating gate by enlarging the capacity area. An unvolatile storage device for increasing the coupling ratio consists of a substrate with a complex number of isolation areas, a first conductive layer formed on the substrate and isolation area. A pair of sidewalls of the first conductive layer is vertically in each isolation area the said vertical sidewall is covered with curtain by a dielectric layer etched with vertical edge. A second conductive layer is formed on the first conductive layer and is isolated with the first one by an interface to increase the surface area and the coupling ratio. An internal conductive dielectric layer is formed in the middle between the first and second conductive layers.

Description

technical field [0001] The present invention relates to a non-volatile memory (Non-Volatile Memory, NVM), and in particular to a non-volatile storage device with an increased coupling ratio (Coupling Ratio), which is achieved by increasing the capacitance area, so that the The control gate voltage required for program and erase efficiency can be reduced. [0002] The invention also relates to a method of manufacturing the above device. Background technique [0003] A floating gate erasable memory cell (Erasable Memory Cell), typically includes a field effect transistor (Field Effect Transistor), a floating gate is located above the channel of the field effect transistor, and at least a part of a control gate is located on the floating above the grid. Floating gates and control gates are usually made of polysilicon. As the name of the floating gate indicates, electrons are isolated in the floating gate. For example, the floating gate can be formed in an environment complete...

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Problems solved by technology

[0005] The coupling ratio of the control gate to the floating gate is very important for non-volatile memory. A low coupling ratio requires a high control gate voltage to achieve program and erase efficiency. A high control gate voltage requirement This highlights the difficulties in the design of charge pumps. Moreover, the high control gate voltage requirements also hinder the reduction of oxide thickness and channel length of high voltage devices.

In order to counteract this shortcoming of a high voltage requirement, there are several ways to increase the coupling ratio. For example, the thickness of the dielectric layer can be reduced. Another method is to increase the dielectric constant of the inner polysilicon. However, reducing the dielectric The thickness of the layer is limited by the lifetime of the data retention, plus increasing the dielectric constant of the inner polysilicon usually requires the development of new materials

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