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Gate dielectric material lanthanum silicate film with high dielectric coefficient as well as preparation method and use thereof

A technology of high dielectric coefficient and gate dielectric, applied in the field of microelectronic materials, can solve the problems of easy deliquescence and deterioration, can not fully meet all requirements, and achieve the effect of high thermodynamic stability

Inactive Publication Date: 2010-02-03
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But none of them can completely satisfy the replacement of SiO 2 all requirements of
La 2 o 3 It has a high dielectric constant (k≈30) and a large forbidden band width (E g ≈5.5eV) but because it is easy to absorb moisture and CO in the air 2 And it is easy to deliquesce and deteriorate, forming hydroxide or carbonate of La; while SiO 2 It is an excellent gate dielectric material, which can limit its further application due to its small dielectric coefficient (k≈3.9)

Method used

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  • Gate dielectric material lanthanum silicate film with high dielectric coefficient as well as preparation method and use thereof
  • Gate dielectric material lanthanum silicate film with high dielectric coefficient as well as preparation method and use thereof
  • Gate dielectric material lanthanum silicate film with high dielectric coefficient as well as preparation method and use thereof

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Embodiment Construction

[0048] Preparation of high dielectric gate dielectric materials (La 2 o 3 ) x (SiO 2 ) 1-x The molar ratio of the substance is 1: 1, and its preparation steps are as follows:

[0049] (1) Preparation of LSO ceramic target material 5: pure La 2 o 3 and SiO 2 The powders are mixed according to the molar ratio of 1:1, fully milled by a ball mill for 24 hours, and the mixed powder is cold pressed into a Φ25×4mm disc under a pressure of 13Mpa, and the disc is sintered at 1500°C for 6 hours in a box-type resistance furnace , to obtain a dense white LSO ceramic target;

[0050] (2) Selection and treatment of substrate material: p-type Si(100) is selected, and the resistivity is 1-50Ω·cm. First put the p-type Si(100) substrate into acetone or absolute ethanol for ultrasonic cleaning for 5 minutes, then use deionized water for ultrasonic cleaning for 5 minutes, and then use a molar ratio of 1:25 hydrofluoric acid solution to etch away the surface of the silicon wafer. A layer ...

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Abstract

The invention discloses a gate dielectric lanthanum silicate film with high dielectric coefficient, a preparation method and application thereof. The chemical formula of the film is (La2O3) x (SiO2) 1-x, wherein x is more than or equal to 0.4 and less than or equal to 0.6. The preparation method of the film comprises the following steps: a KrF excimer laser (1) is started to focalize a pulse laserbeam on an LSO porcelain target (5) through a focusing lens (2); pulse laser is used to strip off the LSO porcelain target (5); the generated laser plasma is deposited on a silicon substrate materialso as to prepare the lanthanum silicate film; the lanthanum silicate film is a an amorphous film of which the physical thickness is 5 nanometers, the dielectric constant is 16.9, the thickness of anequivalent oxide is 1.11 nanometers and the leakage current is 21.7A / cm<2>; moreover, the lanthanum silicate film has higher thermodynamic stability; and no boundary layer is generated. The lanthanumsilicate film can be used in a gate dielectric material of a metal-oxide-semiconductor field effect transistor.

Description

technical field [0001] The invention belongs to the field of microelectronic materials, and in particular relates to a lanthanum silicate thin film of a high-permittivity gate dielectric material used in a metal-oxide-semiconductor field effect transistor (MOSFET) and a preparation method thereof. Background technique [0002] In silicon-based semiconductor integrated circuits, metal-oxide-semiconductor field effect transistors (MOSFETs) are the basic units that constitute memory units, microprocessors, and logic circuits. Its volume is directly related to the integration degree of VLSI. According to the famous Moore's Law, the integration level of integrated circuits will double every 18 months, and the feature size will shrink. times. According to the prediction of the International Semiconductor Technology Roadmap (ITRS) published by the International Semiconductor Industry Association in 1999, the 0.1μm photolithography technology will become mature by 2005, and the S...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/51H01L29/78H01L21/285H01L21/314C23C14/28C23C14/54C23C14/06
Inventor 高立刚国洪轩夏奕东殷江刘治国
Owner NANJING UNIV