Making method for grid structure

Abstract

A grid structure manufacturing method comprises the following steps: depositing on substrate in a sequence with dielectric layer, conducting layer, blocking layer and patterned photoinduced corrosion resist layer; etching blocking layer; removing the patterned photoinduced corrosion resist layer; using the primary etching gas to etch the conducting layer surface; using the secondary etching gas to etch the conducting layer and the dielectric layer. By setting the etching rates of the etching gas on the conducting layer material and the conducting layer upper metal oxide layer respectively, an etching selection ratio of the etching gas on the conducting layer material and the conducting layer upper metal oxide layer can be obtained, finally, a grid structure without bottom defect can be obtained.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a gate structure. Background technique [0002] Semiconductor devices change the electric field strength in the dielectric layer by applying a voltage on the gate, and then control the electric field on the surface of the substrate, and finally change the conductivity of the conductive channel. It can be seen that the performance of the gate is very important to the performance of the semiconductor device, and the performance of the gate is mainly determined by the structure of the gate. [0003] 1A to 1D are device cross-sectional schematic diagrams illustrating each step of the manufacturing method of the gate structure in the prior art. The method is: [0004] First, as shown in FIG. 1A , a dielectric layer 20 , a conductive layer 30 , a barrier layer 40 and a patterned photoresist layer 50 are sequentially deposited on a substr...

AI Technical Summary

Problems solved by technology

Then, the root defect of the barrier layer will serve as a hard mask for etching the conductive layer and the dielectric layer at the same time, so that the etching gas cannot etch the conductive layer and the dielectric layer under the root defect of the barrier layer, forming a gate root defect

The existence of the root defect of the gate is equivalent to increasing the length of the gate, and the increase of the gate length is likely to cause a decrease in device performance, such as a decrease in drain saturation current, a decrease in threshold voltage, and an increase in interjunction capacitance. will cause device failure

Images