Semiconductor device grids preparation method

Abstract

The invention provides a method for manufacturing a grid of a semiconductor part, which comprises the steps as follows: a dielectric layer is formed on a semiconductor substrate; a heteromorphic silicon layer is formed on the dielectric layer; a mask layer is formed on the heteromorphic silicon layer and is graphed to define the location of the grid; the mask layer and the heteromorphic silicon layer are sculptured to form the grid; a polymer which is oxidized and sticks to a root segment of the grid; the oxidized polymer is wiped off by wet; the mask layer is removed then. The method of the invention can obtain the grid with good shape and outline, and suits for manufacturing the grid in particular to a characteristic size of line width below 65nm.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a metal oxide semiconductor (MOS) device gate. Background technique [0002] In order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, the density of components is developing towards higher integration, and the gate structure of semiconductor devices is becoming thinner and longer. Ever shorter. After the manufacturing process enters the 65nm process node, the minimum line width of the gate can reach 40nm. In this case, the manufacture of the gate plays a crucial role in the performance of the MOS device. [0003] Polysilicon is the preferred material for manufacturing gates, which has special heat resistance and high etching pattern accuracy. The manufacturing method of the gate first needs to form a layer of gate silicon oxide on the semiconductor substrate, then deposi...

AI Technical Summary

Problems solved by technology

However, in the above process, due to the influence of process conditions, lateral tensile stress will be generated in the gate oxide layer 110 formed by thermal oxidation growth or CVD process, and the polysilicon deposited near the surface of the gate oxide layer 110 will be affected. Under the influence of the above stress, the lattice structure is stretched, so that the atomic structure of this part of polysilicon is slightly changed compared with the upper layer of polysilicon, so that during plasma etching, the bottom layer of the polysilicon layer 120 close to the gate oxide layer 110 There is a difference in the reaction of the part and the upper part far away from the gate oxide layer 110 to the etching effect of the plasma, resulting in the root 150 phenomenon (footing) at the bottom of the polysilicon layer 120

The existence of such root defects will affect the line width characteristic dimension of the gate, especially when the gate width of the 65nm technology node is extremely small, even a root with a width of only 1nm will have an adverse effect on the line width characteristic dimension of the gate. Change the effective channel length of the gate and destroy the device performance

Images