Method for enhancing self-aligning contact hole breakdown voltage and polysilicon gate construction

Abstract

The invention discloses a method for improving breakdown voltage for a self-aligning contact hole, which comprises the following steps: 1, depositing polycrystalline silicon, an oxidation film layer and a hard mask layer on an oxide layer on a silicon substrate in turn; 2, etching the hard mask layer, the oxidation film layer and the polycrystalline silicon from the top down in turn to form a polycrystalline silicon gate, and making a top angle at the top of the polycrystalline silicon become circular; 3, growing an oxidation film layer on the lateral surface of the polycrystalline silicon gate; 4, growing a side wall; and 5, etching the self-aligning contact hole. A polycrystalline silicon structure comprises a polycrystalline silicon layer, the oxidation film layer and the hard mask layer from the bottom up in turn. The oxidation film layer as a polycrystalline silicon gate structure is arranged between the hard mask layer and the polycrystalline silicon layer, the top angle at the top of the polycrystalline silicon gate is made to be circular, and the thicker oxidation film and nitride film are formed at the top angle of the top of the grate, so as to improve the breakdown voltage performance for the self-aligning contact hole.

Description

technical field [0001] The invention relates to the technical field of semiconductor inheritance circuit manufacturing, in particular to a method for improving the breakdown voltage of a self-aligned contact hole, and a polysilicon gate structure for realizing the method. Background technique [0002] The contact hole is a path connecting the front-end device and the back-end wiring, and its breakdown voltage performance is an important electrical parameter of the integrated circuit. In some memory circuits, a self-aligned contact hole process is often utilized to increase circuit density and process window. When the distance between the gate lines is very small or the alignment process of the self-aligned contact hole deviates, the contact hole after optical development will partially sit on the gate spacer layer, and the plasma will Experience a certain amount of damage to the gate sidewall. This reduces the effective distance from the top corner of the gate to the conta...

AI Technical Summary

Problems solved by technology

like Figure 4 As shown, after the self-aligned contact hole etching process, when the alignment process of the self-aligned via hole deviates, the via etching process will damage the top corner of the gate sidewall, resulting in the loss of the sidewall dielectric material , so that the distance between the top corner of the gate and the via hole is reduced

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