Etching and filling method of deep groove isolation structure of silicon-on-insulator

Abstract

The invention provides an etching and filling method of a deep groove isolation structure of silicon-on-insulator. The invention comprises a buried oxide layer which is arranged on a semiconductor substrate and N-shaped top layer monocrystal silicon which is arranged on the buried oxide layer. The technology process in particular is as follows: (1) adopting the ion reactive etching process to etch a deep groove of which the groove width is 20% greater than that of the target groove width; (2) carrying out low pressure chemical vapor deposition on the N-shaped heavy doping monocrystal silicon;(3) adopting the ion reactive etching process to etch a deep groove structure in the N-shaped heavy doping monocrystal silicon; (4) thermally growing on the insulation oxide layer by a wet-oxygen method, wherein the thickness of the isolation oxide layer depends on the requirements of the isolation performance; and (5) depositing the polysilicon to ensure that the whole groove is completely filled. In the deep groove technology of silicon-on-insulator of the invention, interface charge is introduced between the deep groove structure isolation oxide layer and the silicon film of silicon-on-insulator, therefore, the lateral breakdown voltage between the active region and the groove region is improved, and simultaneously, under the condition that the identical breakdown voltage is ensured, the minimum spacing between the active region and the groove region is shortened and the integration density is improved.

Description

technical field [0001] The invention belongs to the field of power semiconductor integrated circuits, in particular to an etching and filling method for a deep groove all-dielectric isolation structure on a silicon-on-insulator (SOI) material. Background technique [0002] In high and low voltage power integrated circuits, one of the biggest challenges is to achieve complete isolation of high and low voltage parts. Because the high-voltage and low-voltage circuits are made on the same substrate, the carriers injected into the substrate by the device will be collected by the adjacent large-area power devices, which may cause false turn-on of the power device, which limits the integration of high-voltage and low-voltage circuits. a major factor. The ideal method for device isolation would be to completely enclose each device in an insulating material. With the increasing maturity of SOI (silicon-on-insulator) bonding technology, the silicon-on-insulator deep trench isolation...

AI Technical Summary

Problems solved by technology

However, amorphous silicon will still produce lattice defects during the recrystallization process, and the transition zone between the silicon layer and the isolation oxide layer is not obvious, which will affect the electrical isolation characteristics of the deep trench

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