High-low voltage device for plasma display driving chip and preparation method

Abstract

The invention provides a high-low voltage device for a plasma display driving chip and a preparation method. The device comprises a high-voltage N-type lateral isolation gate bipolar type transistor, a high-voltage P-type lateral double diffused metal oxide semiconductor field effect transistor, a high-voltage N-type lateral double diffused metal oxide semiconductor field effect transistor, a high-voltage diode and a low-voltage device. The preparation method comprises the following steps of: making a buried oxide layer and depositing a P-type epitaxial layer on the P-type substrate; making a high-voltage N-well and a high-voltage P-well of the high-voltage device on the P-type epitaxial layer; then making P-type body areas of the high-voltage N-type lateral isolation gate bipolar type transistor and the high-voltage P-type lateral double diffused metal oxide semiconductor field effect transistor on the P-type epitaxial layer; and making all low-voltage wells on the P-type epitaxial layer. The chip structure in the invention has the advantages of low chip power consumption, small chip area and high reliability, and can be compatible with manufacture technology of a standard low-voltage complementary type metal oxide semiconductor field effect transistor.

Description

technical field [0001] The invention relates to a high-voltage and low-voltage device for a display driving chip and a preparation method thereof, and is especially suitable for a row addressing driver chip and a column addressing driver chip for a plasma display (Plasma Display Panel, PDP). Background technique [0002] The plasma display is controlled and driven by the row driver chip and the column driver chip to realize the display of the image. The internal circuit of the chip is composed of low-voltage logic control circuit and high-voltage output drive device, among which the high-voltage output drive device directly lights up and controls the PDP display. With the continuous improvement of the design level and process manufacturing level of the driver chip, the characteristics of low cost, high frequency, high reliability, and low power consumption have become the development direction of the display driver chip. The manufacturing process of low-voltage logic contro...

AI Technical Summary

Problems solved by technology

The traditional isolation method is mainly based on bulk silicon PN junction isolation or single-slot isolation, in which the PN isolation structure occupies more than 20% of the chip area, while the single-slot isolation occupies a small area of ​​the chip and can be controlled within 5%. However, there are still deficiencies in the reliability of the isolation

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