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Method for preparing via hole

A technology of vias and graphics, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of medium surface damage, engraved, not engraved, etc., to reduce process costs, easy to operate, The effect of simple process

Active Publication Date: 2012-04-11
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This etch process creates vias in the dielectric but also damages the surface of the dielectric
The etching depth of this process is not easy to control, and it is easy to cause over-etching and under-etching.

Method used

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  • Method for preparing via hole
  • Method for preparing via hole
  • Method for preparing via hole

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Embodiment Construction

[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0032] The method for preparing via holes provided by the present invention is realized by photolithography, and the process of etching gate dielectric is omitted. In this process, after the preparation of the gate electrode of the device is completed, in order to achieve the interconnection between the gate electrode and the lead wires on the gate dielectric to be grown later, the via hole pattern is first photoetched on the gate electrode, and then the interconnection metal is evaporated, and finally Regenerate the gate dielectric material. The thickness of the metal via hole is greater than that of the gate dielectric, so the gate dielectric can be exposed. In this way, it is very convenient to connect with the source...

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Abstract

The invention discloses a method for preparing a via hole, comprising the following steps: coating photoresist on an insulating substrate; photoetching to obtain gate electrode patterns; electron beam evaporating or PECVD depositing metal electrodes; stripping a needless gold thin film by acetone to obtain the gate electrode patterns of a device; photoetching again to obtain via hole patterns after dividing glue on the gate electrode; electron beam evaporating via hole metal; depositing gate dielectric materials after stripping; photoetching again to obtain interconnected glue patterns on gate dielectric; electron beam evaporating connection metal; and realizing the interconnection of the upper conducting wire and the lower conducting wire of the gate electrode after stripping. The methodsaves the technological process of etching gate dielectric. After the preparation of the gate electrode of a device is finished, in order to achieve the interconnection of the gate electrode and a lead wire on gate dielectric to grow subsequently, firstly the via hole patterns are photoetched on the gate electrode, then interconnect metal is evaporated, and finally gate dielectric materials re-grow. The preparation process of the via hole has simple technology, operability is more convenient than an etching method, and the technology cost is reduced.

Description

technical field [0001] The invention relates to the technical field of microfabrication in organic semiconductors, in particular to a method for preparing via holes in the manufacture of organic field effect transistors. Background technique [0002] With the continuous deepening of information technology, electronic products have entered every aspect of people's life and work; in daily life, people's demand for low-cost, flexible, low-weight, and portable electronic products is increasing; traditional inorganic semiconductor-based It is difficult for devices and circuits of materials to meet these requirements, so organic microelectronics technology based on organic polymer semiconductor materials that can realize these characteristics has received more and more attention under this trend. [0003] Improving the performance of organic field effect transistors has always been a goal pursued by this field. In addition to the material and device structure having a great influ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L51/40
Inventor 刘舸刘明刘兴华商立伟王宏柳江
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI