Method for preparing via hole
A technology of vias and graphics, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of medium surface damage, engraved, not engraved, etc., to reduce process costs, easy to operate, The effect of simple process
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[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.
[0032] The method for preparing via holes provided by the present invention is realized by photolithography, and the process of etching gate dielectric is omitted. In this process, after the preparation of the gate electrode of the device is completed, in order to achieve the interconnection between the gate electrode and the lead wires on the gate dielectric to be grown later, the via hole pattern is first photoetched on the gate electrode, and then the interconnection metal is evaporated, and finally Regenerate the gate dielectric material. The thickness of the metal via hole is greater than that of the gate dielectric, so the gate dielectric can be exposed. In this way, it is very convenient to connect with the source...
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