Precharge type phase-frequency detector

Abstract

The invention discloses a precharge type phase-frequency detector, which comprises a precharge type phase-frequency detection circuit connected with a high resistance elimination circuit. The high resistance elimination circuit consists of a first phase inverter, a second phase inverter, a third phase inverter, a first P-type MOS tube, a second P-type MOS tube, a first N-type MOS tube, a second N-type MOS tube and a third N-type MOS tube which are connected. On the basis of the common precharge type phase-frequency detector, the high resistance elimination circuit is arranged, so on the one hand, high resistance nodes are eliminated, the output node clock of the circuit is connected to a power supply or earthed, the output node level is always definite level at any time and the antijamming capability of the circuit is greatly improved, on the other hand, the output level deviation caused by current competition is eliminated in the process that input signals are changed from high to low, and the output level is restored into standard level.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, in particular to a pre-charging type frequency and phase detector with high anti-interference ability. Background technique [0002] Frequency and phase detectors are widely used in the design of phase-locked loop circuits to complete the frequency and phase comparison between the input reference signal and the output signal of the frequency divider, detect the frequency or phase difference between the two, and provide input for the subsequent circuit Signal. In the phase-locked loop circuit that requires fast locking, the frequency of the phase-locked loop reference signal is usually relatively high, and the pre-charged frequency discriminator has been widely used because of its fast speed. [0003] figure 1 It is a transistor-level circuit diagram of a commonly used pre-charged frequency and phase detector. The two output terminals of this circuit will be in a high-impedance stat...

AI Technical Summary

Problems solved by technology

[0005] To sum up, during the transition process of the input signal from high level to low level, current competition and clock feedthrough will occur in the corresponding output branch, making the output signal deviate from the standard level; during the low level period of the input signal , the corresponding output node is in a high-impedance state, the signal level is a weak level, and the node has no anti-interference ability

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