Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure

A two-frequency divider and ultra-wideband technology, which is applied in the field of two-frequency divider structure, can solve the problems of high power consumption and insufficient working bandwidth of CML frequency band, and achieve the effects of low power consumption, widening operating frequency range and convenient design.

Inactive Publication Date: 2010-12-22
FUDAN UNIV
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Problems solved by technology

It is precisely because of the use of this load that the CML's frequency band working b

Method used

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  • Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure
  • Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure
  • Complementary metal oxide semiconductor (CMOS) ultra-wide-band divide-by-2 frequency divider structure

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Embodiment Construction

[0022] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0023] figure 1 It is a structural block diagram of a frequency divider with a CML structure. The structure contains two master-slave differential D latches, the two latches are connected in the form of negative feedback, and the input clock is a differential signal and , can be a sinusoidal signal or a square wave signal. Output two pairs of quadrature differential signals: and , and . In the positive half cycle of the clock, the main latch works in the following state, and its output , follow input , ;The slave latch works in the latched state, and its output remains unchanged, which is the output of the previous clock phase , . In the negative half cycle of the clock, the main latch works in the latched state, and its output remains unchanged, which is the output of the previous clock phase , ;The slave latch works in the fol...

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Abstract

The invention belongs to the technical field of clock frequency division, in particular relates to a divide-by-2 frequency divider structure based on a standard complementary metal oxide semiconductor (CMOS) process and suitable for an ultra-wide band. The divide-by-2 frequency divider consists of two primary and secondary differential analog D latches, wherein each D latch is a dynamic bias taking a pair of differential N-channel metal oxide semiconductor (NMOS) tubes as an amplifying part, a pair of crossly coupled positive feedback NMOS tubes as a latching part, a pair of p-channel metal oxide semiconductor (PMOS) tubes as a load and a pair of clocked NMOS tubes as the amplifying part and the latching part respectively; the magnitude of the bias voltage of the PMOS tubes changes along with frequencies; and a frequency-voltage converting circuit provides a bias for the PMOS tube load. The divide-by-2 frequency divider structure can effectively increase the working frequency range of a frequency divider; and the ratio of an upper limit frequency to a lower limit frequency of the divide-by-2 frequency divider structure can reach about 250. The circuit of the invention has the characteristics of low power consumption and noise, high speed and the like.

Description

technical field [0001] The invention belongs to the technical field of clock frequency division, and in particular relates to a two-frequency divider structure suitable for ultra-wideband based on a standard CMOS process. Background technique [0002] With the development of broadband wireless communication technology, high-performance clock circuit has increasingly become the bottleneck of the further development of this technology. As one of the key modules of the high-frequency frequency synthesizer, the high-frequency frequency divider mainly functions to divide the highest clock frequency of the system by two, and output quadrature I and Q signals as required. In addition, it can divide high-speed non-50% duty cycle signals into 50% duty cycle signals by two. It not only determines the highest operating frequency of the system, but also its performance will directly affect the phase noise and power consumption of the phase-locked loop circuit and so on. [0003] Curre...

Claims

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Application Information

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IPC IPC(8): H03L7/18
Inventor 梅年松洪志良
Owner FUDAN UNIV
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