Low power-consumption time-delay controllable POR (power on reset) method and circuit

Abstract

The invention relates to a low power-consumption time-delay controllable POR (power on reset) method and circuit. Impulse waveform signals are generated through changing the input control end Vc of a programmable oscillator, wherein the period of the impulse waveform signals is T1; a counter counts the impulse waveform signals, and when the count value of the counter reaches a set value m, the output of the counter is changed from a logic low level into a logic high level; and an output buffer circuit outputs the logic high level as a POR signal, namely the time delay (Tdelay) required for realizing POR is m*T1, and the programmable oscillator and the counter are shut by utilizing the logic high level output by the buffer circuit. By utilizing the low power-consumption time-delay controllable POR method and circuit, the technical problems that the existing POR circuit is difficult to reach the delay of millisecond magnitude and can not change the time delay interval under the condition of not adopting off-chip capacitance are solved; and the time delay value can be programmed and changed, the delay of millisecond magnitude can be realized, and the circuit only has tiny instant power consumption.

Description

technical field [0001] The invention belongs to the field of electricity, and relates to a power-on reset method and circuit, in particular to a power-on reset method and circuit of a power management circuit in a CMOS integrated circuit. Background technique [0002] In the power management circuit, the power-on reset circuit Power On Reset (POR) provides a reset signal for the circuit. The power-on reset circuit is used to ensure that the circuit will not cause system errors due to instability of the power supply voltage at the initial stage of power-on. Usually, the power-on reset circuit is required to output a valid signal after a certain delay time after the power supply voltage exceeds the detection threshold, so as to ensure that the circuit works under a stable power supply voltage condition. [0003] figure 1 Shown is a schematic diagram of a common power-on reset circuit at present, and the circuit is mainly composed of a voltage detection circuit, a delay circu...

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Problems solved by technology

[0006] figure 1 For the power-on reset circuit shown, if the on-chip integrated resistors and capacitors are used to realize the delay, because the on-chip capacitance density is very small, only pf-level capacitance can be realized in the case of a reasonable layout area, and the delay of millisecond level cannot be achieved.

This requires the use of nF-level or uF-level capacitors outside the chip to achieve delays. The disadvantage of this is that it increases the number of package pins and peripheral devices; at the same time, because the on-chip resistance and capacitance values ​​are fixed, it is difficult Change the delay of the power-on reset circuit by programming

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