Floating gates of EEPROM (electrically erasable programmable read-only memory) and manufacturing method thereof

Abstract

The invention discloses a manufacturing method of floating gates of an EEPROM (electrically erasable programmable read-only memory). The method comprises the following steps: 1. etching a polysilicon layer on the surface of a silicon wafer to form floating gates, wherein the side walls of the floating gates have angle of inclination being 70-80 degrees; and the silicon wafer is characterized in that gate oxide layers and tunnelling oxide layers have been formed on the silicon substrate; isolation structures have existed in the silicon substrate; and the polysilicon layer has been deposited onthe surface of the silicon substrate; 2. growing silicon oxide layers on the surfaces of the floating gates by adopting the thermal oxide growth process; and 3. depositing a silicon nitride layer anda silicon oxide layer on the surface of the silicon wafer in sequence, wherein the silicon oxide layers, the silicon nitride layers and the silicon oxide layers on the floating gates form ONO (oxide-nitride-oxide) layers. The topography of the floating gates after etching becomes oblique through improvement and the upper angles of the floating gates are chamfered through the thermal oxide growth process, thus improving the data retention of the EEPROM.

Description

technical field [0001] The invention relates to a manufacturing method of a semiconductor integrated circuit device, in particular to a manufacturing method of an EEPROM. Background technique [0002] see figure 1 , which is a schematic cross-sectional view of the EEPROM array in the word line direction, which shows an EEPROM memory cell, including a storage transistor and a selection transistor. Both transistors are fabricated on substrate 10 and gate oxide 11 . The memory transistor therein also includes a tunnel oxide layer 11 a which is thinner than the gate oxide layer 11 in a small area. The memory transistor also includes a floating gate 12 located below, an ONO (Oxide-Nitride-Oxide) layer 13 located in the middle, and a control gate 14 located above. When the control gate 14 is etched, the ONO layer 13 and the floating gate 12 are etched away together to form isolation between the storage transistor and the selection transistor. [0003] see figure 2 , which is...

AI Technical Summary

Problems solved by technology

When the floating gate 12 has a vertical etching profile, it is easy to form an acute angle on the upper corner of the floating gate 12, which will cause the bottom silicon oxide of the ONO layer 13 to have an uneven film thickness at the edge of the floating gate 12, thereby affecting the ONO layer 13. The effect of blocking electrons

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