Manufacturing method of gates of EEPROM (Electrically Erasable Programmable Read-Only Memory) and gates manufactured by using same

Abstract

The invention discloses a manufacturing method of gates of an EEPROM (Electrically Erasable Programmable Read-Only Memory). The manufacturing method comprises the following steps of: 1, depositing undoped polysilicon on the surface of a silicon wafer, wherein the silicon wafer is provided with an isolation region and a p well, the p well is provided with at least one n-type heavily doped region which defines a channel length of a floating gate transistor, the surface of the silicon wafer is provided with gate oxide layers of a selection transistor and a high voltage transistor, and a tunneling oxide layer of the floating gate transistor; 2, carrying out n-type impurity ion implantation on the polysilicon, wherein the ion implantation amount is 1*1015-2*1015 atoms per square centimeter; and 3, etching the n-type doped polysilicon to form gates of the selection transistor and the high voltage transistor and a floating gate of the floating gate transistor. The manufacturing method of the gate of the EEPROM has the advantages of simple process, low cost and capability of avoiding plasma injury of the tunneling oxide layer.

Description

technical field [0001] The present invention relates to an NVM (non-volatile memory, non-volatile memory), in particular to an EEPROM (Electrically-Erasable Programmable Read-Only Memory, electrically erasable programmable read-only memory). Background technique [0002] see figure 1 , the existing EEPROM memory cell is composed of a selection transistor 1a and a floating gate tunnel oxide layer transistor (FLOTOX, FLOating gate Tunnel OXide, sometimes simply referred to as a floating gate transistor) 1b. Wherein, the selection transistor 1a is usually an NMOS, and performs a gate function; the floating gate transistor 1b is usually an n-channel MOS transistor, and performs a data storage function. The floating gate transistor 1b comprises two gates 13a, 13b, with the floating gate 13a below and the control gate 13b above. The floating gate 13a extends above the drain 11, and the oxide layer between the floating gate 13a and the drain 11 is very thin (for example ), call...

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Problems solved by technology

At this time, the plasma for removing the photoresist will cause serious plasma damage to the tunnel oxide layer 24a of the floating gate transistor 1b

[0012] The gate manufacturing method of the above-mentioned EEPROM performs second doping on the polysilicon of the selection transistor and the high-voltage transistor through an additional photolithography and ion implantation process, so that the doping concentration of the polysilicon gate of the selection transistor and the high-voltage transistor is greater than that of the floating gate transistor Polysilicon floating gate doping concentration, which makes the manufacturing cost higher

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