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Soft IP core of HDLC (high-level data link control) protocol controller

A protocol controller and soft core technology, applied in the direction of data exchange, digital transmission system, electrical components, etc. through path configuration, it can solve the problem that the communication method cannot meet the requirements, and achieve rich diversity, reduce costs, and shorten cycle times. Effect

Inactive Publication Date: 2011-09-14
HARBIN UNIV OF SCI & TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As electronic products become more and more advanced, boards are becoming more and more complex, and the capacity and reliability requirements for data transmission between boards and between boards and terminals are also getting higher and higher. Simple communication methods can not meet the requirements

Method used

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  • Soft IP core of HDLC (high-level data link control) protocol controller
  • Soft IP core of HDLC (high-level data link control) protocol controller
  • Soft IP core of HDLC (high-level data link control) protocol controller

Examples

Experimental program
Comparison scheme
Effect test

specific Embodiment approach 1

[0017] Specific implementation mode one: combine figure 1 Describe this embodiment, this embodiment comprises Avalon bus interface module 1, control module 2, receiving channel 3 and transmission channel 4;

[0018] The Avalon bus interface module 1 is used to send the data stream on the Avalon bus to the transmission channel 4 under the control signal of the control module 2, and is also used to send the original data stream of the receiving channel 3 to the transmission channel 4 under the control signal of the control module 2. on the Avalon bus;

[0019] The control module 2 is used to control the flow of data flow between modules, that is, to control the correct transmission of data flow between modules, and to coordinate and control the work of the entire system;

[0020] The receiving channel 3 is used to receive the data stream on the HDLC bus under the control signal of the control module 2, and restore the data stream on the HDLC bus to the original data stream;

...

specific Embodiment approach 2

[0022] Specific implementation mode two: combination figure 2 Describe this embodiment, the first difference between this embodiment and the specific embodiment is that the receiving channel 3 includes an HDLC frame detection module 31, a "0" module 32, a receiving channel CRC check module 33, a serial-to-parallel conversion module 34 and a receiving channel FIFO Module 35;

[0023] HDLC frame detection module 31, is used to detect whether there is the start frame of the HDLC protocol that conforms to in the data flow on the HDLC bus, then receive this data flow, and send to delete " 0 " module 32, otherwise continue to detect; The frame is "01111110" frame;

[0024] Delete "0" module 32, used to delete a "0" inserted in every five consecutive "1"s in the received data stream, and send the data stream after deleting "0" to the receiving channel CRC check Module 33, this module is to restore the data stream that conforms to the HDLC protocol to a normal data stream to ensure...

specific Embodiment approach 3

[0029] Specific implementation mode three: combination image 3 Describe this embodiment, the difference between this embodiment and the specific embodiment 1 or 2 is that the transmission channel 4 includes a transmission channel FIFO module 41, a parallel-to-serial conversion module 42, a transmission channel CRC check module 43, a "0" insertion module 44 and packaging HDLC module 45;

[0030] The transmission channel FIFO module 41 is used for buffering the data flow, waiting for the control signal of the control module 2 to receive the data flow of the Avalon bus interface module 1, and send it to the parallel-to-serial conversion module 42;

[0031] Parallel-to-serial conversion module 42, used to convert the received data stream from parallel data to serial data, and send the converted data stream to the transmission channel CRC check module 43;

[0032] The transmission channel CRC verification module 43 is used to perform CRC verification on the converted data stream,...

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Abstract

The invention discloses a soft IP core of an HDLC (high-level data link control) protocol controller, relating to the field of design of integrated circuits and aiming at being capable of applying the HDLC protocol controller in an SOPC (system on programmable chip) system. The soft IP core comprises an Avalon bus interface module (1), a control module (2), a receiving channel (3) and a transmission channel (4), wherein the Avalon bus interface module (1) is used for transmitting a data stream on an Avalon bus to the transmission channel (4); the transmission channel (4) is used for receiving the data stream and converting the data stream into a data stream meeting an HDLC protocol, and transmitting the converted data stream to an HDLC data bus; the receiving channel (3) is used for receiving the data stream on the HDLC bus and reducing the data stream on the HDLC bus into an original data stream; the Avalon bus interface module (1) is also used for transmitting the original data stream of the receiving channel (3) to the Avalon bus; and the control module (2) is used for controlling the data stream to flow among all the modules. The traditional transmission interface equipment based on the HDLC protocol is directly connected to a developed system, and thus not only the development cycle is reduced, but also the development resource is saved.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an IP soft core of an HDLC protocol controller. Background technique [0002] Advanced Data Link Control (High-Level Data Link Control or HDLC for short) is a bit-oriented data link layer protocol for transmitting data on a synchronous network. As electronic products become more and more advanced, boards are becoming more and more complex, and the capacity and reliability requirements for data transmission between boards and between boards and terminals are also getting higher and higher. Simple communication methods Can't meet the requirements. The bit-oriented synchronous data control protocol HDLC has the following characteristics: [0003] The protocol does not depend on any character encoding set; [0004] Data packets can be transparently transmitted, and the "0-bit insertion method" used for transparent transmission is easy to implement in hardware; [0005] Fu...

Claims

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Application Information

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IPC IPC(8): H04L12/56H04L12/40
Inventor 王建民曹一江徐基鑫谢应东王伟君
Owner HARBIN UNIV OF SCI & TECH