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Method for forming alternative arrangement of P-type and N-type semiconductor thin layers

An N-type semiconductor, alternate arrangement technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of lower breakdown voltage and high cost, and achieve the effect of improving breakdown voltage

Active Publication Date: 2011-11-23
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem with this method is that the cost is higher
But because the bottom of groove 35 does not contact silicon substrate 31 under normal circumstances (see image 3 ), the N-type silicon epitaxial layer 32 between the bottom of the trench 35 and the silicon substrate 31 will not be completely depleted during operation, which will lead to a decrease in breakdown voltage

Method used

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  • Method for forming alternative arrangement of P-type and N-type semiconductor thin layers
  • Method for forming alternative arrangement of P-type and N-type semiconductor thin layers
  • Method for forming alternative arrangement of P-type and N-type semiconductor thin layers

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Experimental program
Comparison scheme
Effect test

Embodiment 1

[0036] A highly doped N-type impurity substrate silicon wafer 51 is used. On this substrate silicon chip 51, grow the N-type thick epitaxial layer 52 of low doping (referring to Figure 4 ), the thickness of the epitaxial layer 52 is between 40.0 μm-50.0 μm. One or several layers of silicon oxide are grown on the upper surface of the epitaxial layer 52 as a mask for trench etching, and a trench 55 with a depth of 35.0-50.0 μm is etched in the epitaxial layer 52 (see Figure 5 ). The silicon oxide mask can be removed or left after trench etching. If the silicon oxide mask is kept, during the subsequent process of silicon epitaxial growth filling the trench 55, by adjusting the ratio of the flow rate of the silicon source and the flow rate of the halide gas, the effect that silicon does not grow on the surface of the silicon oxide can be achieved. After the trench 55 is etched, the trench 55 is filled with a P-type silicon epitaxial growth process.

[0037] When the trench 5...

Embodiment 2

[0041] Adopt the N-type impurity substrate silicon wafer 51 with high doping, grow the N-type thick epitaxial layer 52 of low doping on this substrate silicon wafer 51 (referring to Figure 4 ), the thickness of the epitaxial layer 52 is between 40.0 μm-50.0 μm. One or several layers of silicon oxide are grown on the upper surface of the epitaxial layer 52 as a mask for trench etching, and a groove 55 with a depth of 35.0-50.0 μm is etched in the epitaxial layer 52 (see Figure 5 ).

[0042] The silicon oxide mask can be removed or left after trench etching. If the silicon oxide mask is kept, during the subsequent process of silicon epitaxial growth filling the trench 55, by adjusting the ratio of the flow rate of the silicon source and the flow rate of the halide gas, the effect that silicon does not grow on the surface of the silicon oxide can be achieved. After the trench 55 is etched, the trench 55 is filled with a P-type silicon epitaxial growth process.

[0043] When ...

Embodiment 3

[0047] Adopt the N-type impurity substrate silicon wafer 51 with high doping, on this substrate silicon wafer 51, grow the N-type thick epitaxial layer 52 of low doping (referring to Figure 4 ), the thickness of the epitaxial layer 52 is between 40.0 μm-50.0 μm. One or several layers of silicon oxide films are grown on the upper surface of the epitaxial layer 52, and the silicon oxide films can prevent silicon epitaxy from growing on the surface of the trench during subsequent silicon epitaxial filling, and prevent the trench from being sealed prematurely during the filling process, thereby Reduce the difficulty of trench filling. Using photoresist as a mask for trench etching, etch a trench 55 with a depth of 35.0-50.0 μm in the epitaxial layer 52 (see Figure 5 ). The photoresist is removed after the trench 55 is etched. The trench 55 is filled with a P-type silicon epitaxial growth process.

[0048] When the trench 55 is filled by the P-type silicon epitaxial growth pr...

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Abstract

The invention discloses a method for forming alternative arrangement of P-type and N-type semiconductor thin layers, comprising the following steps: growing an epitaxial layer on a silicon wafer substrate; forming a groove on the epitaxial layer; and adopting a silicon source gas, hydrogen, a halide gas and a gas-doped mixed gas to carry out inverted silicon epitaxial growth in the groove so as to fill the groove, wherein when the silicon epitaxial growth is carried out, the growth rate of a side wall at the bottom of the groove is more than that of a side wall at the top of the groove, and the dosage concentration at the bottom of the groove is higher than that of any other part in the groove. The method is utilized to exhaust the epitaxial layer below the bottom of the groove and improve the breakdown voltage of a device, and can be applied to super junction MOS (metal oxide semiconductor) devices.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a method for forming alternately arranged P-type and N-type semiconductor thin layers. Background technique [0002] Superjunction MOSFET devices such as figure 1 As shown, in the epitaxial layer 2 on the silicon substrate (N+ silicon substrate) 1, there is a trench-type epitaxial layer 3 filled with the opposite conductivity type, and the top of this region is sequentially covered by the P well region 5 and the N+ well Region 6, surrounded by P+ injection layer 7. Between the two trench-type epitaxial layers 3 and on the N epitaxial layer 2 is provided polysilicon 4 , an interlayer dielectric 8 is provided on the polysilicon 4 , and a source metal electrode 9 covers the entire interlayer dielectric 8 and the epitaxial layer 3 . On the back side of the silicon substrate 1 there is a back metal electrode (drain) 10 . [0003] The main difficulty of the device is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/18H01L21/205
CPCH01L21/0262H01L29/7802H01L29/1095H01L21/0243H01L29/0634H01L21/02532H01L21/0245H01L21/02576H01L21/02636
Inventor 刘继全肖胜安
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP