Floating gate structure of flash memory device and manufacturing method for floating gate structure

Abstract

Provided are a float gate structure for a flash memory device and a preparation method thereof. An H-shaped float gate is formed by changing the preparation method of the float gate in the standard flash memory process, adding a three-step deposit, two-step etching, and one-step chemical-mechanical polishing (CMP). Other steps except the above are the same as the standard flash memory process. The coupling coefficient can be improved effectively without adding additional photoetching plates or increasing process complexity, thus reducing the crosstalk between adjacent devices, and this plays an important role in improving the programming speed and reliability of flash memory.

Description

technical field [0001] The invention belongs to the technical field of non-volatile memory in ultra-large scale integrated circuit manufacturing technology, and specifically relates to a floating flash memory that can increase the coupling coefficient of flash memory, reduce crosstalk between adjacent units, reduce operating voltage, and improve its reliability. Gate structure and its preparation method. Background technique [0002] Flash memory is the mainstream technology of non-volatile memory nowadays. It has the advantages of being able to retain data even when power is off, good compatibility with CMOS technology, and rewritable data multiple times. It is widely used in various products. Such as storage and communication devices such as mobile phones, notebooks, handheld computers and solid state drives. Flash memory usually uses polysilicon floating gate to store data (charge), and the flash memory cell and its floating gate structure are usually as figure 1 As sho...

AI Technical Summary

Problems solved by technology

However, as the size of the flash memory device shrinks sharply, the distance between adjacent cells shrinks sharply. In order to reduce the crosstalk between adjacent cells, the thickness of the floating gate is also greatly reduced, resulting in a gap between the floating gate and the control gate. The area of ​​the dielectric layer is rapidly reduced, so the capacitance value Cono is also greatly reduced

In this way, the coupling coefficient shrinks as the size of the flash memory device shrinks, which brings difficulty in reducing the operating voltage and poor anti-interference performance.

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