Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
A gate and dielectric layer technology, applied in the field of manufacturing high dielectric constant dielectric gate structures, can solve the problems of reducing channel mobility, process complexity and reducing device drive current, etc.
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[0010] refer to figure 1 , to obtain a bulk substrate (bulk substrate) 100 . The bulk substrate 100 may include, but is not limited to, selected from single crystal silicon lightly doped with n-type or p-type dopants, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide ( InP) or indium antimonide (InSb) materials. Alternatively, the semiconductor layer may be formed on an insulating layer to make a silicon-on-insulator (SOI) or equivalent SiGe-on-insulator, Ge-on-insulator, or III-V (such as GaAs, InP, InSb) structures on insulator structures. Gate pre-cleaning may be performed on the surface of the substrate 100 .
[0011] A plasma nitridation process is used to form the nitrided interface layer 200 . The plasma nitridation process may be performed at about room temperature to 500° C., at a pressure of about 1 millitorr (mT) to 1 atmosphere (atm), at a pressure of about 10 watts (W) to 2000 W, and may employ nitrogen (N2) or ammonia ( NH3)....
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