Check patentability & draft patents in minutes with Patsnap Eureka AI!

Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors

A gate and dielectric layer technology, applied in the field of manufacturing high dielectric constant dielectric gate structures, can solve the problems of reducing channel mobility, process complexity and reducing device drive current, etc.

Inactive Publication Date: 2012-03-07
IBM CORP
View PDF2 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the capping layer will significantly reduce the channel mobility, thereby reducing the drive current of the device in addition to additional process complexity and cost

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
  • Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors
  • Method and structure for threshold voltage control and drive current improvement for high-k metal gate transistors

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0010] refer to figure 1 , to obtain a bulk substrate (bulk substrate) 100 . The bulk substrate 100 may include, but is not limited to, selected from single crystal silicon lightly doped with n-type or p-type dopants, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide ( InP) or indium antimonide (InSb) materials. Alternatively, the semiconductor layer may be formed on an insulating layer to make a silicon-on-insulator (SOI) or equivalent SiGe-on-insulator, Ge-on-insulator, or III-V (such as GaAs, InP, InSb) structures on insulator structures. Gate pre-cleaning may be performed on the surface of the substrate 100 .

[0011] A plasma nitridation process is used to form the nitrided interface layer 200 . The plasma nitridation process may be performed at about room temperature to 500° C., at a pressure of about 1 millitorr (mT) to 1 atmosphere (atm), at a pressure of about 10 watts (W) to 2000 W, and may employ nitrogen (N2) or ammonia ( NH3)....

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

Description

technical field [0001] The present invention relates generally to integrated circuits, and more particularly to methods of fabricating high-permittivity (high-k) dielectric gate structures with interfacial nitridation to adjust threshold voltage and improve drive current. Background technique [0002] Integrated circuits often employ active devices known as transistors such as field effect transistors (FETs). A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) includes a silicon-based substrate including a pair of impurity regions (ie, a source junction and a drain junction) separated by a channel region. Above the channel region, gate electrodes are separated by a dielectric. The junction may include a dopant of the opposite type to the dopant present in the channel region. MOSFETs that include n-type doped junctions are called NFETs. A MOSFET that includes a p-type doped junction is called a PFET. The gate electrode may serve as a mask for the channel region d...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
CPCH01L21/28176H01L21/28185H01L21/28202H01L29/495H01L29/4966H01L29/513H01L29/517H01L2924/0002H01L2924/00
Inventor 卜惠明M.P.查德齐克何卫R.贾金容熙S.A.克里什南R.T.莫N.莫门W.C.纳兹勒
Owner IBM CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More