PIN device in bipolar complementary metal oxide semiconductor (BiCMOS) process

Abstract

The invention discloses a PIN device in a bipolar complementary metal oxide semiconductor (BiCMOS) process. The PIN device is formed on a P-type silicon substrate; an active region is isolated through a shallow slot field oxide; and on an overlook surface, the layout structure of the PIN device is octagonal, polygonal over octagonal or round. On a cross section, the PIN device comprises an N-typeregion, an I-type region and a P-type region, wherein the N-type region consists of a shallow slot field oxide bottom of two sides of the active region and an N-type embedded layer in a transverse distance away from the active region and is led out through deep hole contact; the I-type region consists of an N-type collector implantation region formed in the active region; and the P-type region consists of an intrinsic base region epitaxial layer which is formed on the surface of the active region and doped with P-type impurities. The series resistance of the device can be effectively reduced,the forward conduction current of the device is improved, the current of the device is more uniform in each direction, and the properties of the device are improved.

Description

Technical field [0001] The invention relates to a semiconductor integrated circuit device, in particular to a PIN device in a BiCMOS process. Background technique [0002] The existing Bipolar Transistor in the BiCMOS process uses a highly doped collector buried layer to reduce collector resistance, and a high concentration and high energy N-type implant is used to connect the collector buried layer to form a collector. Collector pick-up. The low-doped collector region is epitaxially on the buried layer of the collector region, and the base region is formed by the P-type doped epitaxy in place, and then the N-type heavily doped polysilicon forms the emitter, and finally completes the fabrication of the Bipolar Transistor. Such as figure 1 As shown, it is a schematic diagram of the cross-sectional structure of the first PIN device in the existing BiCMOS process. The first existing PIN device includes: an N-type region, an I-type region, and a P-type region; the N-type region is ...

AI Technical Summary

Problems solved by technology

so image 3 The series resistance at the four corner regions of the shown rectangle or square is larger than the series resistance at the four sides, which will make the current of the forward conductor of the existing second PIN device uneven in all directions

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