Low Voltage Differential Signal Transmitter
A low-voltage differential signal and transmitter technology, applied to the shaping network in the transmitter/receiver, baseband system components, etc., can solve the problem of increased power consumption, large quiescent current, and instability of the common-mode level of the output differential signal, etc. problem, to achieve the effect of saving area and power consumption
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Embodiment 1
[0052] As a possible implementation mode, the specific circuit of a low-voltage differential signal transmitter in Embodiment 1, its circuit structure schematic diagram is as follows Figure 6 shown.
[0053] The low voltage differential signal transmitter includes a mirror module 1 and an output module 2 .
[0054] The mirror module 1 includes a mirror current unit 12 , an auxiliary circuit and a mirror circuit unit 11 .
[0055] NMOS transistor M 5 with resistor R 1 The mirror circuit unit 11 is configured in series.
[0056] In mirror module 1, NMOS (N-type Mental-Oxide-Semiconductor) transistor M 5 The channel width-to-length ratio is W / L; the resistance R 1 The resistance is R up .
[0057] Mirror current unit 12 is a mirror current source, and the current size of mirror current unit 12 bias is 1 ref .
[0058] Resistance R 1 one end of the M 5 connected to the source, the resistor R 1 The other end of the mirror current unit 12 is connected to the output of t...
Embodiment 2
[0100] As another possible implementation, Embodiment 2 of the present invention also proposes a second schematic diagram of a circuit structure of a low-voltage differential signal transmitter, as shown in Figure 7 shown.
[0101] The low-voltage differential signal transmitter of Embodiment 2 includes a mirror module 1 and an output module 2 .
[0102] The mirror module 1 includes a mirror current unit 12 , an auxiliary circuit unit 13 and a mirror circuit unit 11 .
[0103] PMOS transistor M 5 with resistor R 1 The mirror circuit unit 11 is configured in series.
[0104] In mirror block 1, the PMOS transistor M 5 The channel width-to-length ratio is W / L, and the resistance R 1 The resistance is R up ;
[0105] Described mirror current unit 12 is a mirror current source, and its bias current value size is 1 ref .
[0106] Resistance R 1 One end of the transistor M 5 connected to the source, the resistor R 1 The other end of the mirror current unit 12 is connecte...
Embodiment 3
[0152] As another possible implementation mode, Embodiment 3 of the present invention also proposes a third schematic diagram of a circuit structure of a low-voltage differential signal transmitter, as shown in Figure 8 shown.
[0153] The low-voltage differential signal transmitter of the third embodiment includes a mirror module 1 and an output module 2 .
[0154] The mirror module 1 includes a mirror current unit 12 , an auxiliary circuit unit 13 and a mirror circuit unit 11 .
[0155] NMOS transistor M 6 with PMOS transistor M 5 The mirror circuit unit 11 is configured in series.
[0156] In mirror block 1, the NMOS transistor M 6 The channel width to length ratio is (W / L) 1 , PMOS transistor M 5 The channel width to length ratio is (W / L) 2 .
[0157] Described mirror current unit 12 is a mirror current source, and its bias current value size is 1 ref .
[0158] Transistor M 6 The drain of the transistor is connected to the power supply voltage VCC, and the tra...
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