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Production method of shallow trench isolation

A fabrication method and shallow trench technology, which are used in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as the inability to meet the performance of PMOS devices, and reduce power consumption, increase mobility, and improve response speed. Effect

Active Publication Date: 2015-01-28
SEMICON MFG INT (SHANGHAI) CORP +1
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Problems solved by technology

However, with the development of IC technology, only the method of implanting heavy metal atoms into the surface of the active region to make the surface of the active region non-crystalline can no longer meet the performance requirements of PMOS devices.

Method used

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  • Production method of shallow trench isolation
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  • Production method of shallow trench isolation

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specific Embodiment 1

[0029] In the prior art, silicon material is often used as a substrate, which is called a silicon substrate. The silicon substrate may be an n-type silicon substrate whose doping type is electron type or a p-type silicon substrate whose doping type is hole type. Taking a wafer (Wafer) with a silicon substrate as an example below, combined with Figure 2-7 ,Detailed description figure 1 The STI manufacturing method of the NMOS device of the present invention shown, its steps are as follows:

[0030] Step 101, figure 2 It is a schematic cross-sectional structure diagram of step 101 of the STI manufacturing method in the present invention, such as figure 2 As shown, a silicon dioxide liner 201 and a silicon nitride layer 202 are sequentially deposited on the device surface of the wafer;

[0031] In this step, in this step, the silicon dioxide liner 201 and the silicon nitride layer 202 are sequentially deposited on the wafer device surface, that is, the silicon dioxide line...

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Abstract

The invention provides a production method of shallow trench isolation. The production method comprises the following steps: heavy metal ion is doped in silicon dioxide for filling a shallow trench, a formed heavy metal ion doped layer and a PMOS (P-channel Metal Oxide Semiconductor) conducting channel made subsequently are in the same horizontal position, the shallow trench isolation with tensile stress is formed by the heavy metal doped layer, then pressure stress is applied to the conducting channel of a PMOS device by an active area, and the mobility of carriers in the conducting channel of the PMOS device is enhanced, thereby reducing the power consumption of the PMOS and increasing the response speed of the PMOS device.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a shallow trench isolation manufacturing method. Background technique [0002] Current semiconductor integrated circuit (IC) devices are generally fabricated on a substrate. IC devices typically include various discrete circuit elements. In order to isolate discrete circuit components so that each discrete circuit component can work independently and will not be affected by the state of other components, before fabricating IC devices, the substrate is first divided into active areas (Active Area, AA) isolated from each other , and then make discrete circuit components in AA. With the improvement of the integration level of IC devices, shallow trench isolation (Shallow Trench Insulation, STI) technology is usually used to form STI in the substrate. A typical discrete circuit element is a Metal-Oxide Semiconductor Field Effect Transistor (MOS) device. The structure of the...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/265
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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