Method for manufacturing PMOS (p-channel metal oxide semiconductor) device with improved mobility rate of carriers and structure of PMOS device

Abstract

The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing a PMOS (p-channel metal oxide semiconductor) device with improved mobility rate of carriers and a structure of the PMOS device. The method includes: providing a substrate containing an active area of the PMOS device and peripheral areas, forming a plurality of shallow trench isolation structures in the peripheral areas of the substrate, etching substrates between adjacent shallow trench isolation structures so as to form pull-stressed grooves, and filling compress-stressed materials in the pull-stressed grooves. The method for manufacturing the PMOS device has the advantages that the shape of the device cannot be broken, the performance of the device cannot be interfered by the manufacturing process, requirements for the manufacturing process are low, continuous downsizing of the device is facilitated, and the mobility rate of the carriers is increased so as to improve the performance of the device.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a manufacturing method and device structure of a PMOS device that improves carrier mobility. Background technique [0002] With the development of semiconductor technology, the continuous innovation of semiconductor-related manufacturing processes and the development trend of integrated circuit chips shrinking in proportion to the size, it is inevitable that the constant materials and physical effects of the operation of transistors and other components will be affected. After entering the 40nm process, how to improve device performance and suppress turn-off leakage while achieving high turn-on current has become a core issue in device design. [0003] Research has proved that stress engineering plays an increasingly important role in semiconductor technology and device performance. Stress engineering is widely used in semiconductor devices that improve the carrier...

AI Technical Summary

Problems solved by technology

[0005] A large number of structures and materials have been proposed in the prior art to be applied to semiconductor materials containing tensile stress or compressive stress. For example, in Chinese patent CN102110611A, a contact hole directly above the source region and drain region of NMOS is provided. Form a material with tensile stress properties, such as tungsten, to apply tensile stress to the channel region of NMOS, and then selectively remove all or part of the gate structure layer, thereby applying tensile stress to the channel region of NMOS devices, but This manufacturing process changes the shape and properties of the original device, which interferes with device performance, and the manufacturing process is complicated, which cannot effectively reduce the process cost, and is not conducive to the continuous reduction of device size.

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