Semiconductor-on-insulator and preparation method thereof

Abstract

The invention provides a semiconductor-on-insulator and a preparation method thereof. The preparation method comprises the following steps of: forming a plurality of channels in a first silicon dioxide (SiO2) layer on a first Si substrate; optionally extending semiconductor materials such as germanium (Ge), SixGeyCzSn1-x-y-z and III-V group; filling the channels to form a semiconductor layer, and thus obtaining a high-performance semiconductor layer; bonding a second Si substrate with a second SiO2 layer on the surface of the semiconductor layer; removing the Si substrates and removing SiO2; filling polymethyl methacrylate (PMMA); bonding a third Si substrate with a third SiO2 layer on the lower surface of a structure which is obtained, annealing to expand the PMMA, and peeling the structure by using a peeling process which is simple and cost-saving; and polishing to prepare the semiconductor-on-insulator. The method is compatible with the conventional semiconductor technology, the defects of the semiconductor layer can be overcome by optional extension, the performance of the semiconductor-on-insulator can be improved, and by simple PMMA annealing expansion and peeling processes, cost can be saved. The invention is applicable to industrial production.

Description

technical field [0001] The invention belongs to the field of semiconductors, in particular to a semiconductor on insulator and a preparation method thereof. Background technique [0002] SOI (Silicon-On-Insulator, silicon on insulating substrate) technology introduces a buried oxide layer between the top silicon and the back substrate. By forming a semiconductor thin film on an insulator, the SOI material has the incomparable advantages of bulk silicon: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; The integrated circuit also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and is especially suitable for low-voltage and low-power circuits. Therefore, it can be said that SOI will likely become a deep submicron low-voltage , The mainstream technology of low-power integrated circui...

AI Technical Summary

Problems solved by technology

[0003] However, according to the planning of the International Semiconductor Industry Development Blueprint (ITRS2009), integrated circuits have gradually developed from the era of microelectronics to the era of micro-nanoelectronics. its physical limit

Below the 32nm technology node, especially below 22nm, the structure and materials of transistors will face more challenges

XOI (GOI, III-VOI) materials are one of the important solutions, but compatibility with existing semiconductor processes is a technical problem

[0004] The methods for preparing semiconductor-on-insulator in the prior art are either complicated in process and high in production cost, or there are many defects in the crystal that affect the performance

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