Complementary metal-oxide-semiconductor (CMOS) gate oxide layer forming method

Abstract

The invention relates to a complementary metal-oxide-semiconductor transistor (CMOS) gate oxide layer forming method, which comprises the following steps of: providing a substrate, wherein the substrate comprises an N-channel metal-oxide-semiconductor (NMOS) zone and a P-channel metal oxide semiconductor (PMOS) zone which are parallel; forming an oxide layer on the substrate to serve as a subsequent ion injection barrier layer; photoetching to form a first window of the NMOS zone; carrying out ion injection to form a P trap in the substrate of the NMOS zone; etching to remove the oxide layer in the first window; depositing a first gate oxide layer on the substrate of the NMOS zone and the oxide layer of the PMOS zone, and annealing by fluoride; etching to form a second window of the PMOS zone; carrying out ion injection to form an N trap in the substrate of the PMOS zone; etching to remove the first gate oxide layer and the oxide layer in the second window; and depositing a second gate oxide layer on the surface of the above structure. The NMOS gate oxide layer is annealed by the fluoride to lower an interface defect density between the substrate of the NMOS gate oxide layer and the gate oxide layer, improve the transconductance and improve the performance of the NMOS gate oxide layer, and the PMOS gate oxide layer is not annealed by the fluoride, and the performance of the PMOS gate oxide layer is not affected.

Description

Technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a CMOS gate oxide layer. Background technique [0002] The formation of the CMOS gate oxide layer in the prior art includes the following steps: [0003] In step 101, such as Figure 2a As shown, a substrate 200 is provided, the substrate 200 includes a parallel NMOS region I and a PMOS region II, an oxide layer 201 is formed on the substrate 200, and the oxide layer serves as a barrier layer for subsequent ion implantation; [0004] In step 102, such as Figure 2b As shown, the first photoresist 202 is coated, such as Figure 2c As shown, the first photoresist 202 is lithographically formed to form the first window 202a of the NMOS region I; [0005] In step 103, such as Figure 2d As shown, ion implantation is performed in the first window 202a to form a P-well region 203 in the substrate 200 of the NMOS region I, such as Figure 2e As shown, the oxide layer 201 in the f...

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Problems solved by technology

[0009] The study found that annealing with fluorine gas after forming the gate oxide layer can better repair the dangling bonds at the interface between the substrate and the CMOS gate oxide layer, reduce the interface defect density, and improve the transconductance. At the same time, for NMOS, it can weaken the hot carriers. Injection effect and positive bias temperature coupling effect, but for PMOS, when ion implantation forms PMOS source and drain regions, the implantation source is generally boron fluoride, due to the existence of fluorine ions in the PMOS gate oxide layer, it will cause boron in the source and drain regions Ions are more likely to penetrate the gate oxide layer to reach the interface between the substrate and the CMOS gate oxide layer, affecting the threshold voltage of PMOS, thus causing the instability of the threshold voltage of PMOS

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