Manufacturing method of NMOS (N-channel metal oxide semiconductor) device by stress memorization technique
A technology of stress memory technology and manufacturing method, which is applied in the field of semiconductor manufacturing, can solve problems such as unrealization, and achieve the effect of improving integrity failure
Active Publication Date: 2014-12-10
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0016] In view of this, the technical problem solved by the present invention is: after the peak annealing, under the premise of not destroying the silicon nitride layer deposited on the back of the wafer, it is impossible to completely remove the silicon nitride layer deposited on the device surface of the wafer, and at the same time Silicon substrate that does not damage the NMOS active area
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[0034] Combine below Figure 7 to Figure 11 The cross-sectional schematic diagram of the SMT of the prior art to make the NMOS, the detailed description is as follows Image 6 The SMT manufacturing method of the present invention as shown in the NMOS manufacturing method, the specific steps are as follows.
[0035] like Figure 7 As shown, the STI101 in the silicon substrate of the wafer isolates the silicon substrate into several active regions, and the device surfaces of the two adjacent active regions of the silicon substrate respectively have NMOS devices that have been fabricated, wherein the NMOS devices are The structure includes: a P well 102 formed in a silicon substrate, a stacked gate 106 composed of a gate dielectric layer 104 and a gate 105 grown in sequence on the device surface of the silicon substrate, and a sidewall 107 surrounding the stacked gate 106 and The source and drain electrodes located in the silicon substrate on both sides of the stacked gate 106 (t...
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Abstract
The invention provides a manufacturing method of an NMOS (N-channel metal oxide semiconductor) device by using a stress memorization technique (SMT). The method comprises the following steps of: after depositing silicon nitride layers at a device side and a back side of a wafer, carrying out peak annealing to enable the silicon nitride layers subjected to the pressure stress, subsequently forming a silicon dioxide layer on the surface of the silicon nitride layer at the back side of the wafer; and finally etching and removing the silicon nitride layers on the sides of the wafer device by using a wet method. With the adoption of the method, under the condition that the silicon nitride layers are completely removed and a silicon substrate on the side of the wafer device is not damaged at the same time, the silicon nitride layer on the back side of the wafer is not etched and removed by using the wet method; and the method has the advantages of being low in the manufacturing cost and beneficial for recovering the integrity invalidity of a while grid dielectric layer.
Description
technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a manufacturing method of an NMOS device with stress memory technology. Background technique [0002] At present, the semiconductor manufacturing industry mainly grows devices on the wafer device surface of a silicon substrate. Taking Metal-Oxide Semiconductor Field Effect Transistor (MOS) as an example, the MOS device structure includes an active region. , source, drain and gate, wherein the active region is located in the silicon substrate, the gate is located above the active region, and the active regions on both sides of the stacked gate 106 are respectively ion implanted A source and a drain are formed with a conductive channel below the gate and a gate dielectric layer between the gate and the conductive channel. According to the type of majority carriers in the conductive channel, MOS is divided into PMOS with majority carriers as holes and NMOS with majority carri...
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IPC IPC(8): H01L21/8238
Inventor 李凡张海洋黄怡
Owner SEMICON MFG INT (SHANGHAI) CORP