A method for forming a deep trench super pn junction

Abstract

A method for forming a deep-channel super-PN junction, said method comprising: a deposition step (step 1) of depositing an epitaxial layer (101) on a substrate; a dielectric formation step (step 2) of forming a first dielectric layer (201) and a second dielectric layer (301) on the epitaxial layer (101); a deep channel forming step (step 3) of forming a deep channel (401) on the epitaxial layer (101); a filling step (step 4) of filling in the deep channel (401) with epitaxial material (501) so as fill in the entire deep channel, and exceeding the specified height of the second dielectric layer; an etching step (step 5) of etching the epitaxial material (501), the first dielectric layer (201) and the second dielectric layer (301) by means of an etching gas up to the interface between the first dielectric layer (201) and the epitaxial material (501); and a removal step (step 6) of removing the first dielectric layer (201) and the second dielectric layer (301) so as to achieve planarization of the epitaxial material. Use of the present method enables flattening of silicon by means compatible with existing processes, with the advantages of a simple process, high efficiency, and low process costs, and allows problems of unstable Si device parameters caused by using CMP to be avoided.

Description

technical field [0001] The present invention relates to a semiconductor manufacturing technology, in particular to a manufacturing technology of a deep trench super PN junction (Super Junction). Background technique [0002] In the field of semiconductors, Super Junction technology, which is used to improve the performance of power MOS, plays a very significant role in the high-voltage field. [0003] In the traditional manufacturing process of super PN junction, the methods of deep trench etching, epitaxial filling, and silicon CMP planarization are mainly used. Specifically, the method for forming a super PN junction in the conventional technology includes the following steps: [0004] Step 1: Deposit a single thick epitaxial layer (N-type) on the N+ substrate silicon wafer; [0005] Step 2: Forming deep trenches in the epitaxial layer, specifically, growing a thermal oxide layer, then depositing a silicon nitride layer, and then depositing a plasma-enhanced oxide layer,...

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Problems solved by technology

[0008] However, in the technology using CMP, because the CMP equipment of the general production line is used in the back channel, it cannot be mixed with the equipment for processing the super PN junction. Therefore, the method of manufacturing the super PN junction using CMP planarization must use special CMP equipment As a result, the process control is difficult and the cost is high

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