Etching barrier layer used for copper interconnection and manufacturing method thereof

Abstract

The invention belongs to the technical field of a semiconductor integrated circuit, and particularly relates to an etching barrier layer used for copper interconnection and a manufacturing method thereof. The double etching barrier layers are formed by an ultrathin SiN etching barrier layer and a thick SiCN etching barrier layer, wherein the SiN etching barrier layer is processed by oxygen plasma and ultraviolet light radiation, and the SiCN etching barrier layer has a small dielectric constant value and is rich in carbon content. According to the etching barrier layer and the manufacturing method, not only is the technique process simple, also the current situation that the whole dielectric constant value can be affected due to the existence of the etching barrier layer at present can be improved, so that the delay in an interconnection circuit is reduced, the reliability of the interconnection circuit is promoted, and the manufacturing method is expected to be applied to the production of the etching barrier layer for copper interconnection in future.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a double-layer etching barrier layer for copper interconnection and a manufacturing method thereof. Background technique [0002] Copper interconnection technology refers to the semiconductor manufacturing process technology that uses copper metal materials to replace traditional aluminum metal interconnection materials in the production of semiconductor integrated circuit interconnection layers. With the continuous advancement of VLSI process technology, the feature size of semiconductor devices continues to shrink, and the chip area continues to increase. People are faced with how to overcome the RC (R refers to resistance, C refers to Capacitance) significantly increases the delay problem. In particular, due to the increasing influence of the capacitance between metal wiring lines, the performance of the device is greatly reduced, which h...

AI Technical Summary

Problems solved by technology

However, with the continuous shrinking of technology nodes, from 90nm to the current 22nm process technology node, the SiN etch stop layer will increase the dielectric constant value of the overall insulating layer due to the large dielectric constant value, so that Delay rises across the interconnect circuit

There are proposals to use a double-layer etch stop consisting of a thinner layer of silicon-carbon-nitride (SiCN) with a higher dielectric constant and a thicker layer of carbon-rich SiCN with a lower dielectric constant layer, but the reliability brought by the double-layer etching barrier layer to the entire interconnection circuit is not very ideal, such as the ability to suppress electromigration is not very strong, and the dielectric breakdown performance caused by time is not very ideal, and, Under long-term electrical stress, it will cause cavities in the body, etc.

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