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Method for manufacturing gate structure

A gate structure and structure surface technology, which is applied in the field of semiconductor integrated circuit manufacturing technology, can solve problems such as impact, insufficient stability, and increased cost

Inactive Publication Date: 2013-01-30
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Double patterning technology is to make up for the lack of ordinary lithography machine capabilities, using high-precision alignment to perform two exposures and processes; the first exposure and process form part of the pattern, and the second exposure and process form the rest of the pattern. Graphics, in this way, can double the precision of lithography. This technology is generally used in technology generations below 32nm; due to the two lithography and processes, the cost increases; at the same time, the process is affected by the alignment accuracy, and the stability is insufficient;

Method used

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  • Method for manufacturing gate structure
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  • Method for manufacturing gate structure

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Embodiment Construction

[0025] Figure 1-Figure 5 The process (cross-sectional view) of the method for fabricating a gate structure in Embodiment 1 of the present invention is shown.

[0026] see figure 1 ,

[0027] A substrate 10 is provided; a gate dielectric layer 20 is formed on the substrate 10 ; and a sacrificial layer 30 is deposited on the gate dielectric layer 20 .

[0028] The substrate 10 is a silicon substrate, and two device isolation layers 11 and 12 are formed in the substrate 10 . The two device isolation layers 11 , 12 are generally used to isolate the NMOS region and the PMOS region in the substrate 10 . The device isolation layer is formed by a shallow trench isolation (STI) method. A well 13 is formed between the two device isolation layers 11 , 12 .

[0029] The gate dielectric layer generally adopts oxide, nitride or oxynitride or composite. In this embodiment, silicon oxide is used for the gate dielectric layer 20 . Gate dielectric layer 20 is approximately 200 Angstroms...

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Abstract

The invention relates to a method for manufacturing a gate structure. The method comprises the following steps of: providing a substrate; forming a gate dielectric layer on the substrate; depositing a sacrificial layer on the gate dielectric layer; etching the sacrificial layer to form a groove which is exposed out of the gate dielectric layer, and then depositing a gate conductive layer on the surface of the formed structure; etching the gate conductive layer from top to bottom through an anisotropic etching process until the sacrificial layer is exposed; and removing the sacrificial layer to obtain the gate structure. The method provided by the invention realizes the manufacturing of the gate structure by adopting a side wall forming process, and is especially suitable for being used for manufacturing gate structures of smaller sizes, particularly double-gate structures of smaller sizes.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing technology, and in particular relates to a method for manufacturing a gate structure. Background technique [0002] In integrated circuit technology, the size of key graphics such as gate is an important index to measure the performance of semiconductor devices. The formation of the gate structure generally adopts the method of lithography plus etching. However, when the size of the gate is reduced to below 50nm, even if Resolution Enhancement Technology (RET) is adopted, the traditional lithography method cannot meet the process requirements. [0003] At present, lithography at the key level of the technology generation below 45nm will use immersion (Emersion) lithography or double patterning (Double Patterning). These technologies require expensive equipment or special technological processes, which are costly, complicated and difficult. [0004] For exam...

Claims

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Application Information

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IPC IPC(8): H01L21/28
Inventor 储佳
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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