Method for improving isolation properties of shallow trenches in CMOS (complementary metal oxide semiconductor) process

Abstract

The invention discloses a method for improving isolation properties of shallow trenches in a CMOS (complementary metal oxide semiconductor) process. The method includes steps of providing a semiconductor substrate; removing a barrier layer and a buffer layer of the substrate; oxidizing the surface of the substrate to generate a sacrificial oxide layer to be used as a first protective layer; depositing a second protective layer on the sacrificial oxide layer of the substrate; exposing and developing the substrate with shallow trench structures; adjusting an implantation condition to implant devices and keeping electric results of the devices unchanged after the devices are implanted; and removing a photoresist layer and cleaning the substrate. The shallow trench structures are arranged on the substrate, linear silicon nitride and linear oxide layers are filled in the shallow trench structures, the barrier layer and the buffer layer cover the surface of the substrate, and the surface of the substrate comprises surfaces of the shallow trench structures. The method has the advantages that loss of STI (shallow trench isolation) groove oxide layers can be reduced, the isolation properties of the shallow trenches can be improved, and the yield of products is increased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for improving the performance of shallow trench isolation in a CMOS process. Background technique [0002] In the existing CMOS process, SIN (silicon nitride, Si 3 N 4 ) after removal, it will be first oxidized to form a sacrificial oxide layer (sacrificial oxide), use this sacrificial oxide layer as a protective layer, and at the same time expose and develop for subsequent implantation, after the implantation step is completed, perform plasma cleaning-ASHER (a dry etching method used to remove photoresist), and use WET etch to clean, and repeat similar steps to complete the electrical implantation of the semiconductor device. During the cleaning process using WET etch, the STI groove oxide (divot oxide) will be continuously consumed. [0003] Too much oxide loss in the STI groove will easily lead to polysilicon residue (poly residue) in subsequent polysilic...

AI Technical Summary

Problems solved by technology

In the process of cleaning with WET etch, the STI groove oxide (divot oxide) will be continuously consumed

[0003] Too much oxide loss in the STI groove will easily lead to polysilicon residue (poly residue) in subsequent poly etch, and cause leakage, resulting in low yield of products

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